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rk3188: Priority setting i2s under cpll to fix i2s frac div do not effect, let axi_cpu's pll different with i2s's

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chenxing
2013-07-09 11:08:40 +08:00
parent 25354452dd
commit 981f1d9f96
1 changed files with 7 additions and 3 deletions
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10
arch/arm/mach-rk3188/clock_data.c
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@@ -3413,10 +3413,14 @@ void rk30_clock_common_i2s_init(void)
i2s_rate = 49152000;
}
if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
} else if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
/*
* Priority setting i2s under cpll to fix i2s frac div do not effect, let
* axi_cpu's pll different with i2s's
* */
if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
} else if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
} else {
if(general_pll_clk.rate > codec_pll_clk.rate)
clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);