mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-09 12:17:12 +09:00
rm drivers/fpga/spi_fpga.h
This commit is contained in:
root
@@ -1,514 +0,0 @@
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/*
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defines of FPGA chip ICE65L08's register
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*/
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#ifndef SPI_UART_H
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#define SPI_UART_H
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#define SPI_FPGA_INT_PIN RK2818_PIN_PA4
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#define SPI_DPRAM_BUSY_PIN RK2818_PIN_PA2
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#define SPI_FPGA_STANDBY_PIN RK2818_PIN_PH7
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#define SPI_FPGA_TEST_DEBUG 0
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#if SPI_FPGA_TEST_DEBUG
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#define SPI_FPGA_TEST_DEBUG_PIN RK2818_PIN_PE0
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extern int spi_test_wrong_handle(void);
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#endif
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struct uart_icount {
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__u32 cts;
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__u32 dsr;
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__u32 rng;
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__u32 dcd;
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__u32 rx;
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__u32 tx;
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__u32 frame;
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__u32 overrun;
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__u32 parity;
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__u32 brk;
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};
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struct spi_uart
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{
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struct workqueue_struct *spi_uart_workqueue;
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struct work_struct spi_uart_work;
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struct timer_list uart_timer;
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struct tty_struct *tty;
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struct kref kref;
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struct mutex open_lock;
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struct task_struct *in_spi_uart_irq;
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struct circ_buf xmit;
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struct uart_icount icount;
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spinlock_t write_lock;
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spinlock_t irq_lock;
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unsigned int index;
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unsigned int opened;
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unsigned int regs_offset;
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unsigned int uartclk;
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unsigned int mctrl;
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unsigned int read_status_mask;
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unsigned int ignore_status_mask;
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unsigned char x_char;
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unsigned char ier;
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unsigned char lcr;
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};
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struct spi_gpio
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{
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struct workqueue_struct *spi_gpio_workqueue;
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struct work_struct spi_gpio_work;
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struct timer_list gpio_timer;
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};
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struct spi_i2c
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{
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struct workqueue_struct *spi_i2c_workqueue;
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struct work_struct spi_i2c_work;
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struct timer_list i2c_timer;
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struct i2c_adapter *adapter;
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struct i2c_client *client;
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spinlock_t i2c_lock ;
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unsigned char interrupt;
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unsigned char i2c_data_width[2];
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unsigned int speed[2];
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};
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struct spi_dpram
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{
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struct workqueue_struct *spi_dpram_workqueue;
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struct work_struct spi_dpram_work;
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struct workqueue_struct *spi_dpram_busy_workqueue;
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struct work_struct spi_dpram_busy_work;
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struct timer_list dpram_timer;
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unsigned char *prx;
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unsigned char *ptx;
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unsigned int rec_len;
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unsigned int send_len;
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unsigned int max_rec_len;
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unsigned int max_send_len;
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volatile int apwrite_en;
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unsigned short int dpram_addr;
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struct semaphore rec_sem;
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struct semaphore send_sem;
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wait_queue_head_t recq, sendq;
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struct miscdevice miscdev;
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int (*write_dpram)(struct spi_dpram *, unsigned short int addr, unsigned char *buf, unsigned int len);
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int (*read_dpram)(struct spi_dpram *, unsigned short int addr, unsigned char *buf, unsigned int len);
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int (*write_ptr)(struct spi_dpram *, unsigned short int addr, unsigned int size);
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int (*read_ptr)(struct spi_dpram *, unsigned short int addr);
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int (*write_mailbox)(struct spi_dpram *, unsigned int mailbox);
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int (*read_mailbox)(struct spi_dpram *);
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};
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struct spi_fpga_port {
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const char *name;
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struct spi_device *spi;
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struct mutex spi_lock;
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struct workqueue_struct *fpga_irq_workqueue;
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struct work_struct fpga_irq_work;
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struct timer_list fpga_timer;
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/*spi2uart*/
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#ifdef CONFIG_SPI_UART
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struct spi_uart uart;
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#endif
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/*spi2gpio*/
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#ifdef CONFIG_SPI_GPIO
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struct spi_gpio gpio;
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#endif
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/*spi2i2c*/
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#ifdef CONFIG_SPI_I2C
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struct spi_i2c i2c;
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#endif
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/*spi2dpram*/
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#ifdef CONFIG_SPI_DPRAM
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struct spi_dpram dpram;
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#endif
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};
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#define ICE_CC72 0
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#define ICE_CC196 1
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#define FPGA_TYPE ICE_CC196
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#define SEL_UART 0
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#define SEL_GPIO 1
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#define SEL_I2C 2
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#define SEL_DPRAM 3
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#define READ_TOP_INT 4
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/* CMD */
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#define ICE_SEL_UART (SEL_UART<<6)
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#define ICE_SEL_GPIO (SEL_GPIO<<6)
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#define ICE_SEL_I2C (SEL_I2C<<6)
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#define ICE_SEL_DPRAM (SEL_DPRAM<<6)
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#define ICE_SEL_WRITE (~(1<<5))
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#define ICE_SEL_READ (1<<5)
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#define ICE_SEL_UART_CH(ch) ((ch&0x03)<<3)
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#define ICE_SEL_READ_INT_TYPE (3<<3)
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/*read int type*/
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#define ICE_INT_TYPE_UART0 (~(1<<0))
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#define ICE_INT_TYPE_UART1 (~(1<<1))
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#define ICE_INT_TYPE_UART2 (~(1<<2))
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#define ICE_INT_TYPE_I2C2 (~(1<<3))
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#define ICE_INT_TYPE_I2C3 (~(1<<4))
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#define ICE_INT_TYPE_GPIO (~(1<<5))
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#define ICE_INT_TYPE_DPRAM (~(1<<6))
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#define ICE_INT_I2C_ACK (~(1<<0))
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#define ICE_INT_I2C_READ (~(1<<1))
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#define ICE_INT_I2C_WRITE (~(1<<2))
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/*spi to uart*/
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#define ICE_RXFIFO_FULL (1<<8)
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#define ICE_RXFIFO_NOT_FULL (~(1<<8))
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#define ICE_RXFIFO_EMPTY (1<<9)
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#define ICE_RXFIFO_NOT_EMPTY (~(1<<9))
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#define ICE_TXFIFO_FULL (1<<10)
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#define ICE_TXFIFO_NOT_FULL (~(1<<10))
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#define ICE_TXFIFO_EMPTY (1<<11)
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#define ICE_TXFIFO_NOT_EMPTY (~(1<<11))
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/*spi to gpio*/
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#define ICE_SEL_GPIO0 (0X00<<3) //INT/GPIO0
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#define ICE_SEL_GPIO1 (0X02<<2) //GPIO1
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#define ICE_SEL_GPIO2 (0X03<<2)
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#define ICE_SEL_GPIO3 (0X04<<2)
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#define ICE_SEL_GPIO4 (0X05<<2)
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#define ICE_SEL_GPIO5 (0X06<<2)
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#define ICE_SEL_GPIO0_TYPE (0X00)
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#define ICE_SEL_GPIO0_DIR (0X01)
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#define ICE_SEL_GPIO0_DATA (0X02)
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#define ICE_SEL_GPIO0_INT_EN (0X03)
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#define ICE_SEL_GPIO0_INT_TRI (0X04)
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#define ICE_SEL_GPIO0_INT_STATE (0X05)
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#define ICE_SEL_GPIO_DIR (0X01)
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#define ICE_SEL_GPIO_DATA (0X02)
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/*spi to i2c*/
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typedef enum I2C_ch
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{
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I2C_CH0,
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I2C_CH1,
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I2C_CH2,
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I2C_CH3
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}eI2C_ch_t;
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typedef enum eI2CReadMode
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{
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I2C_NORMAL,
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I2C_NOREG
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}eI2ReadMode_t;
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typedef enum eI2RegType
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{
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I2C_8_BIT,
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I2C_16_BIT
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}eI2RegType_t;
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#define ICE_SEL_I2C_START (0<<0)
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#define ICE_SEL_I2C_STOP (1<<0)
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#define ICE_SEL_I2C_RESTART (2<<0)
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#define ICE_SEL_I2C_TRANS (3<<0)
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#define ICE_SEL_I2C_SMASK (~(3<<0))
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#define ICE_SEL_I2C_CH2 (0<<2)
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#define ICE_SEL_I2C_CH3 (1<<2)
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#define ICE_SEL_I2C_DEFMODE (0<<3)
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#define ICE_SEL_I2C_FIFO (1<<3)
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#define ICE_SEL_I2C_SPEED (2<<3)
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#define ICE_SEL_I2C_INT (3<<3)
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#define ICE_SEL_I2C_MMASK (~(3<<3))
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#define ICE_I2C_SLAVE_WRITE (0<<0)
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#define ICE_I2C_SLAVE_READ (1<<0)
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#define ICE_SEL_I2C_W8BIT (0<<2)
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#define ICE_SEL_I2C_W16BIT (1<<2)
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#define ICE_SEL_I2C_DWIDTH (2<<2)
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#define ICE_I2C_AD_ACK (~(1<<0))
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#define ICE_I2C_WRITE_ACK (~(1<<1))
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#define ICE_I2C_READ_ACK (~(1<<2))
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#define ICE_SEL_I2C_CH2_8BIT (0<<2)
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#define ICE_SEL_I2C_CH2_16BIT (1<<2)
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#define ICE_SEL_I2C_CH2_MIX (2<<2)
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#define ICE_SEL_I2C_CH3_8BIT (4<<2)
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#define ICE_SEL_I2C_CH3_16BIT (5<<2)
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#define ICE_SEL_I2C_CH3_MIX (6<<2)
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#define ICE_SEL_I2C_RD_A (7<<2)
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#define ICE_SEL_I2C_MASK (7<<2)
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#define ICE_SEL_I2C_ACK3 (1<<1)
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#define ICE_SEL_I2C_ACK2 (0<<1)
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#define INT_I2C_WRITE_ACK (2)
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#define INT_I2C_WRITE_NACK (3)
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#define INT_I2C_READ_ACK (4)
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#define INT_I2C_READ_NACK (5)
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#define INT_I2C_WRITE_MASK (~(1<<1))
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#define INT_I2C_READ_MASK (~(1<<2))
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#define ICE_SET_10K_I2C_SPEED (0x01)
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#define ICE_SET_100K_I2C_SPEED (0x02)
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#define ICE_SET_200K_I2C_SPEED (0x04)
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#define ICE_SET_300K_I2C_SPEED (0x08)
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#define ICE_SET_400K_I2C_SPEED (0x10)
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/*spi to dpram*/
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#define ICE_SEL_DPRAM_NOMAL (~(1<<5))
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#define ICE_SEL_DPRAM_SEM (1<<5)
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#define ICE_SEL_DPRAM_READ (~(1<<4))
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#define ICE_SEL_DPRAM_WRITE (1<<4)
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#define ICE_SEL_DPRAM_BL1 (0)
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#define ICE_SEL_DPRAM_BL32 (1)
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#define ICE_SEL_DPRAM_BL64 (2)
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#define ICE_SEL_DPRAM_BL128 (3)
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#define ICE_SEL_DPRAM_FULL (4)
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#define ICE_SEL_SEM_WRITE (0x7F)
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#define ICE_SEL_SEM_READ (0xBF)
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#define ICE_SEL_SEM_WRRD (0x3F)
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typedef void (*pSpiFunc)(void); //<2F><><EFBFBD>庯<EFBFBD><E5BAAF>ָ<EFBFBD><D6B8>, <20><><EFBFBD>ڵ<EFBFBD><DAB5>þ<EFBFBD><C3BE>Ե<EFBFBD>ַ
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typedef void (*pSpiFuncIntr)(int,void *);
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typedef struct
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{
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pSpiFuncIntr gpio_vector;
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void *gpio_devid;
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}SPI_GPIO_PDATA;
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typedef enum eSpiGpioTypeSel
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{
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SPI_GPIO0_IS_GPIO = 0,
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SPI_GPIO0_IS_INT,
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}eSpiGpioTypeSel_t;
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typedef enum eSpiGpioPinInt
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{
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SPI_GPIO_INT_DISABLE = 0,
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SPI_GPIO_INT_ENABLE,
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}eSpiGpioPinInt_t;
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typedef enum eSpiGpioIntType
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{
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SPI_GPIO_EDGE_FALLING = 0,
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SPI_GPIO_EDGE_RISING,
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}eSpiGpioIntType_t;
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typedef enum eSpiGpioPinDirection
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{
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SPI_GPIO_IN = 0,
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SPI_GPIO_OUT,
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SPI_GPIO_DIR_ERR,
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}eSpiGpioPinDirection_t;
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typedef enum eSpiGpioPinLevel
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{
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SPI_GPIO_LOW = 0,
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SPI_GPIO_HIGH,
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SPI_GPIO_LEVEL_ERR,
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}eSpiGpioPinLevel_t;
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#if (FPGA_TYPE == ICE_CC72)
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typedef enum eSpiGpioPinNum
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{
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SPI_GPIO_P0_00 = 0, //GPIO0[0]
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SPI_GPIO_P0_01,
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SPI_GPIO_P0_02,
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SPI_GPIO_P0_03,
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SPI_GPIO_P0_04,
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SPI_GPIO_P0_05,
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SPI_GPIO_P2_00,
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SPI_GPIO_P2_01,
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SPI_GPIO_P2_02,
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SPI_GPIO_P2_03,
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SPI_GPIO_P2_04,
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SPI_GPIO_P2_05,
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SPI_GPIO_P2_06,
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SPI_GPIO_P2_07,
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SPI_GPIO_P2_08,
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SPI_GPIO_P2_09 = 15, //GPIO0[15],the last interrupt/gpio pin
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SPI_GPIO_P3_00 = 16, //GPIO1[0]
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SPI_GPIO_P3_01,
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SPI_GPIO_P3_02,
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SPI_GPIO_P3_03,
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SPI_GPIO_P3_04,
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SPI_GPIO_P3_05,
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SPI_GPIO_P3_06,
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SPI_GPIO_P3_07,
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SPI_GPIO_P3_08,
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SPI_GPIO_P3_09,
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SPI_GPIO_P0_06 = 26,
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SPI_GPIO_I2C3_SCL,
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SPI_GPIO_I2C3_SDA,
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SPI_GPIO_I2C4_SCL,
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SPI_GPIO_I2C4_SDA,
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}eSpiGpioPinNum_t;
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#elif (FPGA_TYPE == ICE_CC196)
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typedef enum eSpiGpioPinNum
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{
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//GPIO0/INT
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SPI_GPIO_P6_00 = 0, //HS_DET input
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SPI_GPIO_P6_01,
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SPI_GPIO_P6_02,
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SPI_GPIO_P6_03,
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SPI_GPIO_P6_04, //CM3605_POUT_L_INT input
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SPI_GPIO_P6_05,
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SPI_GPIO_P6_06, //CHG_OK input
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SPI_GPIO_P6_07, //HP_HOOK input
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SPI_GPIO_P6_08,
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SPI_GPIO_P6_09,
|
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SPI_GPIO_P6_10, //DEFSEL input
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SPI_GPIO_P6_11, //FLASH_WP_INT input
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SPI_GPIO_P6_12, //LOW_BATT_INT input
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SPI_GPIO_P6_13, //DC_DET input
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SPI_GPIO_P3_08,
|
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SPI_GPIO_P3_09 = 15,
|
||||
|
||||
//GPIO1
|
||||
SPI_GPIO_P1_00 = 16, //LCD_ON output
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||||
SPI_GPIO_P1_01, //LCD_PWR_CTRL output
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||||
SPI_GPIO_P1_02, //SD_POW_ON output
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||||
SPI_GPIO_P1_03, //WL_RST_N/WIFI_EN output
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||||
SPI_GPIO_P1_04, //HARDO,input
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||||
SPI_GPIO_P1_05, //SENSOR_PWDN output
|
||||
SPI_GPIO_P1_06, //BT_PWR_EN output
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||||
SPI_GPIO_P1_07, //BT_RST output
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||||
SPI_GPIO_P1_08, //BT_WAKE_B output
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SPI_GPIO_P1_09, //LCD_DISP_ON output
|
||||
SPI_GPIO_P1_10, //WM_PWR_EN output
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SPI_GPIO_P1_11, //HARD1,input
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||||
SPI_GPIO_P1_12, //VIB_MOTO output
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||||
SPI_GPIO_P1_13, //KEYLED_EN output
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||||
SPI_GPIO_P1_14, //CAM_RST output
|
||||
SPI_GPIO_P1_15 = 31, //WL_WAKE_B output
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||||
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||||
//GPIO2
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||||
SPI_GPIO_P2_00 = 32, //Y+YD input
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||||
SPI_GPIO_P2_01, //Y-YU input
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||||
SPI_GPIO_P2_02, //AP_TD_UNDIFED input
|
||||
SPI_GPIO_P2_03, //AP_PW_EN_TD output
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||||
SPI_GPIO_P2_04, //AP_RESET_TD output
|
||||
SPI_GPIO_P2_05, //AP_SHUTDOWN_TD_PMU output
|
||||
SPI_GPIO_P2_06, //AP_RESET_CMMB output
|
||||
SPI_GPIO_P2_07, //AP_CHECK_TD_STATUS input
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||||
SPI_GPIO_P2_08, //CHARGE_CURRENT_SEL output
|
||||
SPI_GPIO_P2_09, //AP_PWD_CMMB output
|
||||
SPI_GPIO_P2_10, //X-XL input
|
||||
SPI_GPIO_P2_11, //X+XR input
|
||||
SPI_GPIO_P2_12, //LCD_RESET output
|
||||
SPI_GPIO_P2_13, //USB_PWR_EN output
|
||||
SPI_GPIO_P2_14, //WL_HOST_WAKE_B output
|
||||
SPI_GPIO_P2_15 = 47, //TOUCH_SCREEN_RST output
|
||||
|
||||
//GPIO3
|
||||
SPI_GPIO_P0_00 = 48, //
|
||||
SPI_GPIO_P0_01,
|
||||
SPI_GPIO_P0_02,
|
||||
SPI_GPIO_P0_03,
|
||||
SPI_GPIO_P0_04,
|
||||
SPI_GPIO_P0_05,
|
||||
SPI_GPIO_P0_06,
|
||||
SPI_GPIO_P0_07,
|
||||
SPI_GPIO_P0_08,
|
||||
SPI_GPIO_P0_09, //FPGAС<41><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD> C5
|
||||
SPI_GPIO_P0_10,
|
||||
SPI_GPIO_P0_11,
|
||||
SPI_GPIO_P0_12,
|
||||
SPI_GPIO_P0_13,
|
||||
SPI_GPIO_P0_14,
|
||||
SPI_GPIO_P0_15 = 63,
|
||||
|
||||
//GPIO4
|
||||
SPI_GPIO_P4_00 = 64,
|
||||
SPI_GPIO_P4_01,
|
||||
SPI_GPIO_P4_02,
|
||||
SPI_GPIO_P4_03,
|
||||
SPI_GPIO_P4_04,
|
||||
SPI_GPIO_P4_05,
|
||||
SPI_GPIO_P4_06, //CHARGER_INT_END input
|
||||
SPI_GPIO_P4_07, //CM3605_PWD output
|
||||
SPI_GPIO_P3_00,
|
||||
SPI_GPIO_P3_01,
|
||||
SPI_GPIO_P3_02,
|
||||
SPI_GPIO_P3_03,
|
||||
SPI_GPIO_P3_04,
|
||||
SPI_GPIO_P3_05,
|
||||
SPI_GPIO_P3_06,
|
||||
SPI_GPIO_P3_07 = 79,
|
||||
|
||||
//GPIO5
|
||||
SPI_GPIO_P4_08 = 80, //CM3605_PS_SHUTDOWN
|
||||
SPI_GPIO_P0_TXD2, //temp
|
||||
|
||||
}eSpiGpioPinNum_t;
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
typedef enum eSpiGpioPinIntIsr
|
||||
{
|
||||
SPI_GPIO_IS_INT = 0,
|
||||
SPI_GPIO_NO_INT,
|
||||
}eSpiGpioPinIntIsr_t;
|
||||
|
||||
extern struct spi_fpga_port *pFpgaPort;
|
||||
extern unsigned int spi_in(struct spi_fpga_port *port, int reg, int type);
|
||||
extern void spi_out(struct spi_fpga_port *port, int reg, int value, int type);
|
||||
|
||||
#if defined(CONFIG_SPI_UART)
|
||||
extern void spi_uart_handle_irq(struct spi_device *spi);
|
||||
extern int spi_uart_register(struct spi_fpga_port *port);
|
||||
extern int spi_uart_unregister(struct spi_fpga_port *port);
|
||||
#endif
|
||||
#if defined(CONFIG_SPI_GPIO)
|
||||
extern int spi_gpio_int_sel(eSpiGpioPinNum_t PinNum,eSpiGpioTypeSel_t type);
|
||||
extern int spi_gpio_set_pindirection(eSpiGpioPinNum_t PinNum,eSpiGpioPinDirection_t direction);
|
||||
extern int spi_gpio_set_pinlevel(eSpiGpioPinNum_t PinNum, eSpiGpioPinLevel_t PinLevel);
|
||||
extern eSpiGpioPinLevel_t spi_gpio_get_pinlevel(eSpiGpioPinNum_t PinNum);
|
||||
extern int spi_gpio_enable_int(eSpiGpioPinNum_t PinNum);
|
||||
extern int spi_gpio_disable_int(eSpiGpioPinNum_t PinNum);
|
||||
extern int spi_gpio_set_int_trigger(eSpiGpioPinNum_t PinNum,eSpiGpioIntType_t IntType);
|
||||
extern int spi_gpio_read_iir(void);
|
||||
extern int spi_request_gpio_irq(eSpiGpioPinNum_t PinNum, pSpiFunc Routine, eSpiGpioIntType_t IntType,void *dev_id);
|
||||
extern int spi_free_gpio_irq(eSpiGpioPinNum_t PinNum);
|
||||
extern int spi_gpio_handle_irq(struct spi_device *spi);
|
||||
extern int spi_gpio_init(void);
|
||||
extern int spi_gpio_register(struct spi_fpga_port *port);
|
||||
extern int spi_gpio_unregister(struct spi_fpga_port *port);
|
||||
#endif
|
||||
#if defined(CONFIG_SPI_I2C)
|
||||
extern int spi_i2c_handle_irq(struct spi_fpga_port *port,unsigned char channel);
|
||||
extern int spi_i2c_register(struct spi_fpga_port *port,int num);
|
||||
extern int spi_i2c_unregister(struct spi_fpga_port *port);
|
||||
#endif
|
||||
#if defined(CONFIG_SPI_DPRAM)
|
||||
extern int spi_dpram_handle_irq(struct spi_device *spi);
|
||||
extern int spi_dpram_register(struct spi_fpga_port *port);
|
||||
extern int spi_dpram_unregister(struct spi_fpga_port *port);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -38,6 +38,11 @@
|
||||
|
||||
#define SPI_GPIO_TEST 0
|
||||
#define HIGH_SPI_TEST 1
|
||||
#if HIGH_SPI_TEST
|
||||
#define USE_SYS_INT 1
|
||||
#else
|
||||
#define USE_SYS_INT 0
|
||||
#endif
|
||||
spinlock_t gpio_lock;
|
||||
spinlock_t gpio_state_lock;
|
||||
spinlock_t gpio_irq_lock;
|
||||
@@ -452,7 +457,7 @@ int spi_free_gpio_irq(eSpiGpioPinNum_t PinNum)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if 0
|
||||
#if (USE_SYS_INT ==0)
|
||||
int spi_gpio_handle_irq(struct spi_device *spi)
|
||||
{
|
||||
int gpio_iir, i;
|
||||
|
||||
Reference in New Issue
Block a user