From 982e655deb1a079300c8dd83b6678922b728e576 Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Thu, 4 Jan 2024 11:39:13 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3568: Add nfc

Change-Id: I3fb8fae8b63925d58e6889af4df80e920b3d4881
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 778752440303..e64cd290436e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -2785,6 +2785,30 @@
 		status = "disabled";
 	};
 
+	nfc: nand-controller@fe330000 {
+		compatible = "rockchip,px30-nfc";
+		reg = <0x0 0xfe330000 0x0 0x4000>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_NANDC>, <&cru NCLK_NANDC>;
+		clock-names = "ahb", "nfc";
+		assigned-clocks = <&cru NCLK_NANDC>;
+		assigned-clock-rates = <150000000>;
+		status = "disabled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		nand@0 {
+			reg = <0>;
+			label = "rk-nand";
+			nand-bus-width = <8>;
+			nand-ecc-mode = "hw";
+			nand-ecc-step-size = <1024>;
+			nand-ecc-strength = <16>;
+			nand-is-boot-medium;
+			rockchip,boot-blks = <8>;
+			rockchip,boot-ecc-strength = <16>;
+		};
+	};
+
 	nandc0: nandc@fe330000 {
 		compatible = "rockchip,rk-nandc-v9";
 		reg = <0x0 0xfe330000 0x0 0x4000>;