diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4c7159c9f105..e0d159ffe18a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -860,6 +860,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rv1126-evb-ddr3-v12-spi-nand.dtb \
 	rv1126-evb-ddr3-v12-spi-nor.dtb \
 	rv1126-evb-ddr3-v12-tb-emmc.dtb \
+	rv1126-evb-ddr3-v12-tb-spi-nor.dtb \
 	rv1126-evb-ddr3-v13.dtb \
 	rv1126-evb-lp3-v10.dtb \
 	rv1126-iotest-v10.dtb \
diff --git a/arch/arm/boot/dts/rv1126-evb-ddr3-v12-tb-spi-nor.dts b/arch/arm/boot/dts/rv1126-evb-ddr3-v12-tb-spi-nor.dts
new file mode 100644
index 000000000000..b3e8c8ebb469
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-evb-ddr3-v12-tb-spi-nor.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+#include "rv1126.dtsi"
+#include "rv11xx-evb-v12.dtsi"
+#include "rv11xx-thunder-boot-spi-nor.dtsi"
+#include "rv11xx-evb-thunder-boot.dtsi"
+
+/ {
+	model = "Rockchip RV1126 EVB DDR3 V12 with spi nor (Thunder Boot)";
+	compatible = "rockchip,rv1126-evb-ddr3-v12-tb-spi-nor", "rockchip,rv1126";
+
+	chosen {
+		bootargs = "loglevel=0 initcall_nr_threads=-1 initcall_debug=0 printk.devkmsg=on root=/dev/rd0 console=ttyFIQ0 snd_aloop.index=7";
+	};
+};
diff --git a/arch/arm/boot/dts/rv11xx-thunder-boot-spi-nor.dtsi b/arch/arm/boot/dts/rv11xx-thunder-boot-spi-nor.dtsi
new file mode 100644
index 000000000000..64b2715b6d20
--- /dev/null
+++ b/arch/arm/boot/dts/rv11xx-thunder-boot-spi-nor.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ */
+
+#include "rv11xx-thunder-boot.dtsi"
+
+/ {
+	thunder_boot_spi_nor: thunder-boot-spi-nor {
+		compatible = "rockchip,thunder-boot-sfc";
+		reg = <0xffc90000 0x4000>;
+		memory-region-src = <&ramdisk_c>;
+		memory-region-dst = <&ramdisk_r>;
+	};
+};