From 994f4d2c330790eb8d1696da53fdcada5aa0cc0e Mon Sep 17 00:00:00 2001
From: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Date: Thu, 2 Mar 2023 11:38:25 +0800
Subject: [PATCH] ARM: dts: rockchip: add usb2phy node for rk3036

This patch add usb2phy node for rk3036.

Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: Icf21cb73d125876b507b18e768f9ff652c1a720e
---
 arch/arm/boot/dts/rk3036.dtsi | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 33092646c064..b290a7700cfa 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -525,6 +525,8 @@
 	grf: syscon@20008000 {
 		compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
 		reg = <0x20008000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
 
 		reboot-mode {
 			compatible = "syscon-reboot-mode";
@@ -554,6 +556,33 @@
 				clocks = <&cru SCLK_GPU>;
 			};
 		};
+
+		usb2phy: usb2-phy@17c {
+			compatible = "rockchip,rk3036-usb2phy";
+			reg = <0x017c 0x0c>;
+			clocks = <&cru SCLK_OTGPHY0>;
+			clock-names = "phyclk";
+			#clock-cells = <0>;
+			clock-output-names = "usb480m_phy";
+			status = "disabled";
+
+			u2phy_otg: otg-port {
+				#phy-cells = <0>;
+				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "otg-bvalid", "otg-id",
+						"linestate";
+				status = "disabled";
+			};
+
+			u2phy_host: host-port {
+				#phy-cells = <0>;
+				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "linestate";
+				status = "disabled";
+			};
+		};
 	};
 
 	acodec: acodec-ana@20030000 {