From 995a5e0ef50543922cb8e6e68dd78cda42ccbe16 Mon Sep 17 00:00:00 2001
From: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Date: Wed, 17 May 2023 14:28:08 +0800
Subject: [PATCH] phy: rockchip: naneng-combphy: Fix CTLE register setting
 error for rk3528

Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: I6a217c1b041f5962c500bb4d03f689ce54a42443
---
 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index f12c6e1ec1bd..b2517e02f2e8 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -480,7 +480,7 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
 		/* Enable adaptive CTLE for USB3.0 Rx */
 		val = readl(priv->mmio + 0x200);
 		val &= ~GENMASK(17, 17);
-		val |= 0x01;
+		val |= 0x01 << 17;
 		writel(val, priv->mmio + 0x200);
 
 		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);