From 99abcb8a310b2a2de8fb9a035dbdb4c812bdd15f Mon Sep 17 00:00:00 2001
From: "ruixuan.li" <ruixuan.li@amlogic.com>
Date: Thu, 21 Mar 2019 00:21:10 +0800
Subject: [PATCH] sm1: emmc run hs200 busmode [1/1]

PD#SWPL-5404

Problem:
emmc report data crc error in hs200 busmode

Solution:
set hs200 co_phase to 2 and did not reset the
hs200 co_phase and tx_phase when adjust tuning is
find the error point in sm1

Verify:
verify pass on sm1_s905d3_ac200

Change-Id: I56aa8eb666fb55641db75878a3488f66c721bd6d
Signed-off-by: ruixuan.li <ruixuan.li@amlogic.com>
---
 drivers/amlogic/mmc/aml_sd_emmc.c    | 26 ++++++++++++++++++++++++++
 drivers/amlogic/mmc/aml_sd_emmc_v3.c |  6 ++++--
 2 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/drivers/amlogic/mmc/aml_sd_emmc.c b/drivers/amlogic/mmc/aml_sd_emmc.c
index a23bc679d3d9..56153f5ef961 100644
--- a/drivers/amlogic/mmc/aml_sd_emmc.c
+++ b/drivers/amlogic/mmc/aml_sd_emmc.c
@@ -3641,6 +3641,32 @@ static struct meson_mmc_data mmc_data_tl1 = {
 	.sdmmc.sdr104.core_phase = 2,
 };
 
+static struct meson_mmc_data mmc_data_sm1 = {
+	.chip_type = MMC_CHIP_SM1,
+	.port_a_base = 0xffe03000,
+	.port_b_base = 0xffe05000,
+	.port_c_base = 0xffe07000,
+	.pinmux_base = 0xff634400,
+	.clksrc_base = 0xff63c000,
+	.ds_pin_poll = 0x3a,
+	.ds_pin_poll_en = 0x48,
+	.ds_pin_poll_bit = 13,
+	.sdmmc.init.core_phase = 3,
+	.sdmmc.init.tx_phase = 0,
+	.sdmmc.init.rx_phase = 0,
+	.sdmmc.calc.core_phase = 0,
+	.sdmmc.calc.tx_phase = 2,
+	.sdmmc.hs.core_phase = 3,
+	.sdmmc.ddr.core_phase = 2,
+	.sdmmc.ddr.tx_phase = 0,
+	.sdmmc.hs2.core_phase = 2,
+	.sdmmc.hs2.tx_phase = 0,
+	.sdmmc.hs4.tx_delay = 0,
+	.sdmmc.sd_hs.core_phase = 3,
+	.sdmmc.sdr104.core_phase = 2,
+	.sdmmc.sdr104.tx_phase = 0,
+};
+
 static const struct of_device_id meson_mmc_of_match[] = {
 	{
 		.compatible = "amlogic, meson-mmc-gxbb",
diff --git a/drivers/amlogic/mmc/aml_sd_emmc_v3.c b/drivers/amlogic/mmc/aml_sd_emmc_v3.c
index 888e2c4272c7..0f02a26407f3 100644
--- a/drivers/amlogic/mmc/aml_sd_emmc_v3.c
+++ b/drivers/amlogic/mmc/aml_sd_emmc_v3.c
@@ -1192,8 +1192,10 @@ tunning:
 		nmatch = aml_sd_emmc_tuning_transfer(mmc, opcode,
 				blk_pattern, host->blk_test, blksz);
 		if (nmatch != TUNING_NUM_PER_POINT) {
-			clkc->core_phase = para->hs2.tx_phase;
-			clkc->tx_phase = para->hs2.core_phase;
+			if (host->data->chip_type != MMC_CHIP_SM1) {
+				clkc->core_phase = para->hs2.tx_phase;
+				clkc->tx_phase = para->hs2.core_phase;
+			}
 			writel(vclk, host->base + SD_EMMC_CLOCK_V3);
 			pr_info("%s:try clock:0x%x>>>rx_tuning[%d] = %d\n",
 				mmc_hostname(host->mmc),