From 99e10612ffbe86ebd16df582b7e4d3fdfda6fc94 Mon Sep 17 00:00:00 2001 From: Wu Liangqing Date: Sat, 5 Dec 2020 21:42:27 +0800 Subject: [PATCH] arm64: dts: rockchip: add rk3568-evb2-lp4x-v10 for rk3568 evb2 Change-Id: Ic8b384e260abf71b4e9f1f030f46105554558892 Signed-off-by: Wu Liangqing --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3568-evb2-lp4x-v10.dts | 8 + .../dts/rockchip/rk3568-evb2-lp4x-v10.dtsi | 362 ++++++++++++++++++ 3 files changed, 371 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 338a55cf041a..010136bec86a 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -82,6 +82,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-k108.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-rkg11.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb2-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dts new file mode 100644 index 000000000000..23f5f036c4b2 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568-evb2-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi new file mode 100644 index 000000000000..5b5b653e413f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include "rk3568.dtsi" +#include "rk3568-evb.dtsi" + +/ { + model = "Rockchip RK3568 EVB1 DDR4 V10 Board"; + compatible = "rockchip,rk3568-ev1-ddr4-v10", "rockchip,rk3568"; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_3v3: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "pcie30_3v3"; + regulator-min-microvolt = <0100000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <0100000 0x0 + 3300000 0x1>; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +/* + * mipi_dphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; +}; + +/* + * mipi_dphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd1_n>; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x3c>; + rx_delay = <0x2f>; + + phy-handle = <&rgmii_phy0>; + status = "disabled"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x26>; + + phy-handle = <&rgmii_phy1>; + status = "disabled"; +}; + +/* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ +>1x { + power-supply = <&vcc3v3_lcd0_n>; +}; + +&i2c4 { + status = "okay"; + + gs_mxc6655xa: gs_mxc6655xa@15 { + status = "okay"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_gpio>; + reg = <0x15>; + irq-gpio = <&gpio3 RK_PD7 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; +}; + +&i2c5 { + status = "disabled"; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&mipi_dphy0 { + status = "okay"; +}; + +&mipi_dphy1 { + status = "disabled"; +}; + +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&pcie30_3v3>; + status = "status"; +}; + +&pcie30phy { + status = "status"; +}; + +&pcie3x2 { + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&pcie30_3v3>; + status = "status"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + mxc6655xa { + mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { + rockchip,pins = ; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_32k: wifi-32k { + rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&pmucru CLK_RTC_32K>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h &wifi_32k>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; +}; + +&sdmmc1 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&wireless_wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + wifi_chip_type = "ap6398s"; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&wireless_bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&pmucru CLK_RTC_32K>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; +};