From 9a42eaaa9d0252a3f78e0036185aff0cb7360964 Mon Sep 17 00:00:00 2001
From: Damon Ding <damon.ding@rock-chips.com>
Date: Wed, 12 Apr 2023 10:31:27 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3588: add pwm interrupt configs for
 oneshot mode

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ic58f3e38df65588f6565529a615f77c82696d641
---
 arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 63b90d49a7a8..e6d593aa3810 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2415,6 +2415,7 @@
 	pwm0: pwm@fd8b0000 {
 		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 		reg = <0x0 0xfd8b0000 0x0 0x10>;
+		interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
 		#pwm-cells = <3>;
 		pinctrl-names = "active";
 		pinctrl-0 = <&pwm0m0_pins>;
@@ -2426,6 +2427,7 @@
 	pwm1: pwm@fd8b0010 {
 		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 		reg = <0x0 0xfd8b0010 0x0 0x10>;
+		interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
 		#pwm-cells = <3>;
 		pinctrl-names = "active";
 		pinctrl-0 = <&pwm1m0_pins>;
@@ -2437,6 +2439,7 @@
 	pwm2: pwm@fd8b0020 {
 		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 		reg = <0x0 0xfd8b0020 0x0 0x10>;
+		interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
 		#pwm-cells = <3>;
 		pinctrl-names = "active";
 		pinctrl-0 = <&pwm2m0_pins>;
@@ -5532,6 +5535,7 @@
 	pwm4: pwm@febd0000 {
 		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 		reg = <0x0 0xfebd0000 0x0 0x10>;
+		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
 		#pwm-cells = <3>;
 		pinctrl-names = "active";
 		pinctrl-0 = <&pwm4m0_pins>;
@@ -5543,6 +5547,7 @@
 	pwm5: pwm@febd0010 {
 		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 		reg = <0x0 0xfebd0010 0x0 0x10>;
+		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
 		#pwm-cells = <3>;
 		pinctrl-names = "active";
 		pinctrl-0 = <&pwm5m0_pins>;
@@ -5554,6 +5559,7 @@
 	pwm6: pwm@febd0020 {
 		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 		reg = <0x0 0xfebd0020 0x0 0x10>;
+		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
 		#pwm-cells = <3>;
 		pinctrl-names = "active";
 		pinctrl-0 = <&pwm6m0_pins>;
@@ -5578,6 +5584,7 @@
 	pwm8: pwm@febe0000 {
 		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 		reg = <0x0 0xfebe0000 0x0 0x10>;
+		interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
 		#pwm-cells = <3>;
 		pinctrl-names = "active";
 		pinctrl-0 = <&pwm8m0_pins>;
@@ -5589,6 +5596,7 @@
 	pwm9: pwm@febe0010 {
 		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 		reg = <0x0 0xfebe0010 0x0 0x10>;
+		interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
 		#pwm-cells = <3>;
 		pinctrl-names = "active";
 		pinctrl-0 = <&pwm9m0_pins>;
@@ -5600,6 +5608,7 @@
 	pwm10: pwm@febe0020 {
 		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 		reg = <0x0 0xfebe0020 0x0 0x10>;
+		interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
 		#pwm-cells = <3>;
 		pinctrl-names = "active";
 		pinctrl-0 = <&pwm10m0_pins>;
@@ -5624,6 +5633,7 @@
 	pwm12: pwm@febf0000 {
 		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 		reg = <0x0 0xfebf0000 0x0 0x10>;
+		interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
 		#pwm-cells = <3>;
 		pinctrl-names = "active";
 		pinctrl-0 = <&pwm12m0_pins>;
@@ -5635,6 +5645,7 @@
 	pwm13: pwm@febf0010 {
 		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 		reg = <0x0 0xfebf0010 0x0 0x10>;
+		interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
 		#pwm-cells = <3>;
 		pinctrl-names = "active";
 		pinctrl-0 = <&pwm13m0_pins>;
@@ -5646,6 +5657,7 @@
 	pwm14: pwm@febf0020 {
 		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 		reg = <0x0 0xfebf0020 0x0 0x10>;
+		interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
 		#pwm-cells = <3>;
 		pinctrl-names = "active";
 		pinctrl-0 = <&pwm14m0_pins>;