From ad94bd47746c5787b542008ba41f23c5af6f6168 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 20 Nov 2015 03:28:36 +0200 Subject: [PATCH 1/9] dt-bindings: create arm/nxp folder and move LPC32xx SoC description to it Create a separate folder for device tree bindings of NXP SoCs devices, and move lpc32xx.txt to it. Acked-by: Rob Herring Signed-off-by: Vladimir Zapolskiy --- Documentation/devicetree/bindings/arm/{ => nxp}/lpc32xx.txt | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename Documentation/devicetree/bindings/arm/{ => nxp}/lpc32xx.txt (100%) diff --git a/Documentation/devicetree/bindings/arm/lpc32xx.txt b/Documentation/devicetree/bindings/arm/nxp/lpc32xx.txt similarity index 100% rename from Documentation/devicetree/bindings/arm/lpc32xx.txt rename to Documentation/devicetree/bindings/arm/nxp/lpc32xx.txt From ef5f885ec93b1e6d51a0ef3f4f98d2015b7cab6f Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 20 Nov 2015 03:05:04 +0200 Subject: [PATCH 2/9] arm: dts: lpc32xx: add device nodes for external oscillators NXP LPC32xx SoC has two external oscillators - one is mandatory and always on 32768 Hz oscillator and one optional 10-20MHz oscillator, which is practically always present on LPC32xx boards, because its presence is needed to supply USB controller clock and by default it supplies ARM and most of the peripheral clocks, LPC32xx User's Manual references it as a main oscillator. The change adds device nodes for both oscillators, frequency of the main oscillator is selected to be 13MHz by default, this variant is found on all LPC32xx reference boards. The device nodes for external oscillators are needed to describe input clocks of LPC32xx clock controller. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index c85cf979725e..a9f2d9ac203f 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -28,6 +28,22 @@ }; }; + clocks { + xtal_32k: xtal_32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32k"; + }; + + xtal: xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <13000000>; + clock-output-names = "xtal"; + }; + }; + ahb { #address-cells = <1>; #size-cells = <1>; From fe86131f9e447b606c40a90124b44a21a40ce54a Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 20 Nov 2015 03:05:05 +0200 Subject: [PATCH 3/9] arm: dts: lpc32xx: add clock controller device node NXP LPC32xx SoC has a clocking and power control unit (CPC) as a part of system control block (SCB). CPC is supplied by two external oscillators and it manages core and most of peripheral clocks, the change adds SCB and CPC descriptions to shared LPC32xx dtsi file. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index a9f2d9ac203f..65023c1ff796 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -247,6 +247,23 @@ compatible = "simple-bus"; ranges = <0x20000000 0x20000000 0x30000000>; + /* System Control Block */ + scb { + compatible = "simple-bus"; + ranges = <0x0 0x040004000 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + + clk: clock-controller@0 { + compatible = "nxp,lpc3220-clk"; + reg = <0x00 0x114>; + #clock-cells = <1>; + + clocks = <&xtal_32k>, <&xtal>; + clock-names = "xtal_32k", "xtal"; + }; + }; + /* * MIC Interrupt controller includes: * MIC @40008000 From 93898eb775e599e96ec34d8bd225a395d0c197e0 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 20 Nov 2015 03:05:06 +0200 Subject: [PATCH 4/9] arm: dts: lpc32xx: add clock properties to device nodes The change adds clock properties to all described peripheral devices, clock ids are taken from dt-bindings/clock/lpc32xx-clock.h Some existing drivers expect to get clock names, in those cases clock-names are added as well. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 41 ++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 65023c1ff796..792468ebec7c 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -13,6 +13,8 @@ #include "skeleton.dtsi" +#include + / { compatible = "nxp,lpc3220"; interrupt-parent = <&mic>; @@ -57,6 +59,7 @@ slc: flash@20020000 { compatible = "nxp,lpc3220-slc"; reg = <0x20020000 0x1000>; + clocks = <&clk LPC32XX_CLK_SLC>; status = "disabled"; }; @@ -64,6 +67,7 @@ compatible = "nxp,lpc3220-mlc"; reg = <0x200a8000 0x11000>; interrupts = <11 0>; + clocks = <&clk LPC32XX_CLK_MLC>; status = "disabled"; }; @@ -71,6 +75,8 @@ compatible = "arm,pl080", "arm,primecell"; reg = <0x31000000 0x1000>; interrupts = <0x1c 0>; + clocks = <&clk LPC32XX_CLK_DMA>; + clock-names = "apb_pclk"; }; usb { @@ -110,6 +116,8 @@ compatible = "arm,pl110", "arm,primecell"; reg = <0x31040000 0x1000>; interrupts = <0x0e 0>; + clocks = <&clk LPC32XX_CLK_LCD>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -117,11 +125,14 @@ compatible = "nxp,lpc-eth"; reg = <0x31060000 0x1000>; interrupts = <0x1d 0>; + clocks = <&clk LPC32XX_CLK_MAC>; }; emc: memory-controller@31080000 { compatible = "arm,pl175", "arm,primecell"; reg = <0x31080000 0x1000>; + clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>; + clock-names = "mpmcclk", "apb_pclk"; #address-cells = <1>; #size-cells = <1>; @@ -142,6 +153,8 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x20084000 0x1000>; interrupts = <0x14 0>; + clocks = <&clk LPC32XX_CLK_SSP0>; + clock-names = "apb_pclk"; }; spi1: spi@20088000 { @@ -153,6 +166,8 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x2008c000 0x1000>; interrupts = <0x15 0>; + clocks = <&clk LPC32XX_CLK_SSP1>; + clock-names = "apb_pclk"; }; spi2: spi@20090000 { @@ -169,6 +184,8 @@ compatible = "arm,pl18x", "arm,primecell"; reg = <0x20098000 0x1000>; interrupts = <0x0f 0>, <0x0d 0>; + clocks = <&clk LPC32XX_CLK_SD>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -185,6 +202,7 @@ interrupts = <9 0>; clock-frequency = <13000000>; reg-shift = <2>; + clocks = <&clk LPC32XX_CLK_UART5>; status = "disabled"; }; @@ -194,6 +212,7 @@ interrupts = <7 0>; clock-frequency = <13000000>; reg-shift = <2>; + clocks = <&clk LPC32XX_CLK_UART3>; status = "disabled"; }; @@ -203,6 +222,7 @@ interrupts = <8 0>; clock-frequency = <13000000>; reg-shift = <2>; + clocks = <&clk LPC32XX_CLK_UART4>; status = "disabled"; }; @@ -212,6 +232,7 @@ interrupts = <10 0>; clock-frequency = <13000000>; reg-shift = <2>; + clocks = <&clk LPC32XX_CLK_UART6>; status = "disabled"; }; @@ -222,6 +243,7 @@ #address-cells = <1>; #size-cells = <0>; pnx,timeout = <0x64>; + clocks = <&clk LPC32XX_CLK_I2C1>; }; i2c2: i2c@400A8000 { @@ -231,6 +253,7 @@ #address-cells = <1>; #size-cells = <0>; pnx,timeout = <0x64>; + clocks = <&clk LPC32XX_CLK_I2C2>; }; mpwm: mpwm@400E8000 { @@ -302,6 +325,7 @@ compatible = "nxp,lpc3220-rtc"; reg = <0x40024000 0x1000>; interrupts = <0x34 0>; + clocks = <&clk LPC32XX_CLK_RTC>; }; gpio: gpio@40028000 { @@ -315,6 +339,8 @@ compatible = "nxp,lpc3220-timer"; reg = <0x4002C000 0x1000>; interrupts = <0x3 0>; + clocks = <&clk LPC32XX_CLK_TIMER4>; + clock-names = "timerclk"; status = "disabled"; }; @@ -322,17 +348,22 @@ compatible = "nxp,lpc3220-timer"; reg = <0x40030000 0x1000>; interrupts = <0x4 0>; + clocks = <&clk LPC32XX_CLK_TIMER5>; + clock-names = "timerclk"; status = "disabled"; }; watchdog: watchdog@4003C000 { compatible = "nxp,pnx4008-wdt"; reg = <0x4003C000 0x1000>; + clocks = <&clk LPC32XX_CLK_WDOG>; }; timer0: timer@40044000 { compatible = "nxp,lpc3220-timer"; reg = <0x40044000 0x1000>; + clocks = <&clk LPC32XX_CLK_TIMER0>; + clock-names = "timerclk"; interrupts = <0x10 0>; }; @@ -347,6 +378,7 @@ compatible = "nxp,lpc3220-adc"; reg = <0x40048000 0x1000>; interrupts = <0x27 0>; + clocks = <&clk LPC32XX_CLK_ADC>; status = "disabled"; }; @@ -354,6 +386,7 @@ compatible = "nxp,lpc3220-tsc"; reg = <0x40048000 0x1000>; interrupts = <0x27 0>; + clocks = <&clk LPC32XX_CLK_ADC>; status = "disabled"; }; @@ -361,6 +394,8 @@ compatible = "nxp,lpc3220-timer"; reg = <0x4004C000 0x1000>; interrupts = <0x11 0>; + clocks = <&clk LPC32XX_CLK_TIMER1>; + clock-names = "timerclk"; }; key: key@40050000 { @@ -374,18 +409,22 @@ compatible = "nxp,lpc3220-timer"; reg = <0x40058000 0x1000>; interrupts = <0x12 0>; + clocks = <&clk LPC32XX_CLK_TIMER2>; + clock-names = "timerclk"; status = "disabled"; }; pwm1: pwm@4005C000 { compatible = "nxp,lpc3220-pwm"; reg = <0x4005C000 0x4>; + clocks = <&clk LPC32XX_CLK_PWM1>; status = "disabled"; }; pwm2: pwm@4005C004 { compatible = "nxp,lpc3220-pwm"; reg = <0x4005C004 0x4>; + clocks = <&clk LPC32XX_CLK_PWM2>; status = "disabled"; }; @@ -393,6 +432,8 @@ compatible = "nxp,lpc3220-timer"; reg = <0x40060000 0x1000>; interrupts = <0x13 0>; + clocks = <&clk LPC32XX_CLK_TIMER3>; + clock-names = "timerclk"; status = "disabled"; }; }; From 865e90093af19db18dda7791345bc7b2eb814ade Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 20 Nov 2015 03:05:07 +0200 Subject: [PATCH 5/9] arm: dts: lpc32xx: add USB clock controller The change adds device node of LPC32xx USB clock controller and adds clock properties to USB OHCI, USB device and I2C controller to USB phy device nodes. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 792468ebec7c..db02eb007415 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -92,6 +92,7 @@ compatible = "nxp,ohci-nxp", "usb-ohci"; reg = <0x0 0x300>; interrupts = <0x3b 0>; + clocks = <&usbclk LPC32XX_USB_CLK_HOST>; status = "disabled"; }; @@ -99,6 +100,7 @@ compatible = "nxp,lpc3220-udc"; reg = <0x0 0x300>; interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; + clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; status = "disabled"; }; @@ -106,10 +108,17 @@ compatible = "nxp,pnx-i2c"; reg = <0x300 0x100>; interrupts = <0x3f 0>; + clocks = <&usbclk LPC32XX_USB_CLK_I2C>; #address-cells = <1>; #size-cells = <0>; pnx,timeout = <0x64>; }; + + usbclk: clock-controller@f00 { + compatible = "nxp,lpc3220-usb-clk"; + reg = <0xf00 0x100>; + #clock-cells = <1>; + }; }; clcd: clcd@31040000 { From c82e688a333e41330372bd02478c15660618eb8b Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 20 Nov 2015 03:05:11 +0200 Subject: [PATCH 6/9] arm: dts: lpc32xx: remove clock frequency property from UART device nodes If clock-frequency property is given, then it substitutes calculation of supplying clock frequency from parent clock, this may break UART, if parent clock is given and managed by common clock framework. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index db02eb007415..ba2be0f7d739 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -209,7 +209,6 @@ compatible = "nxp,lpc3220-uart"; reg = <0x40090000 0x1000>; interrupts = <9 0>; - clock-frequency = <13000000>; reg-shift = <2>; clocks = <&clk LPC32XX_CLK_UART5>; status = "disabled"; @@ -219,7 +218,6 @@ compatible = "nxp,lpc3220-uart"; reg = <0x40080000 0x1000>; interrupts = <7 0>; - clock-frequency = <13000000>; reg-shift = <2>; clocks = <&clk LPC32XX_CLK_UART3>; status = "disabled"; @@ -229,7 +227,6 @@ compatible = "nxp,lpc3220-uart"; reg = <0x40088000 0x1000>; interrupts = <8 0>; - clock-frequency = <13000000>; reg-shift = <2>; clocks = <&clk LPC32XX_CLK_UART4>; status = "disabled"; @@ -239,7 +236,6 @@ compatible = "nxp,lpc3220-uart"; reg = <0x40098000 0x1000>; interrupts = <10 0>; - clock-frequency = <13000000>; reg-shift = <2>; clocks = <&clk LPC32XX_CLK_UART6>; status = "disabled"; From b715802f235e27b01786b790cfe5fcd11e6c1ba4 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 20 Nov 2015 03:28:40 +0200 Subject: [PATCH 7/9] arm: dts: lpc32xx: assign interrupt types LPC32xx interrupt controller has two cells, instead of zero specify proper irq types for all consumers. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 63 ++++++++++++++++++---------------- 1 file changed, 34 insertions(+), 29 deletions(-) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index ba2be0f7d739..c58d8da9ea2a 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -14,6 +14,7 @@ #include "skeleton.dtsi" #include +#include / { compatible = "nxp,lpc3220"; @@ -66,7 +67,7 @@ mlc: flash@200a8000 { compatible = "nxp,lpc3220-mlc"; reg = <0x200a8000 0x11000>; - interrupts = <11 0>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_MLC>; status = "disabled"; }; @@ -74,7 +75,7 @@ dma: dma@31000000 { compatible = "arm,pl080", "arm,primecell"; reg = <0x31000000 0x1000>; - interrupts = <0x1c 0>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_DMA>; clock-names = "apb_pclk"; }; @@ -91,7 +92,7 @@ ohci: ohci@0 { compatible = "nxp,ohci-nxp", "usb-ohci"; reg = <0x0 0x300>; - interrupts = <0x3b 0>; + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; clocks = <&usbclk LPC32XX_USB_CLK_HOST>; status = "disabled"; }; @@ -99,7 +100,10 @@ usbd: usbd@0 { compatible = "nxp,lpc3220-udc"; reg = <0x0 0x300>; - interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; + interrupts = <61 IRQ_TYPE_LEVEL_HIGH>, + <62 IRQ_TYPE_LEVEL_HIGH>, + <60 IRQ_TYPE_LEVEL_HIGH>, + <58 IRQ_TYPE_LEVEL_LOW>; clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; status = "disabled"; }; @@ -107,7 +111,7 @@ i2cusb: i2c@300 { compatible = "nxp,pnx-i2c"; reg = <0x300 0x100>; - interrupts = <0x3f 0>; + interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; clocks = <&usbclk LPC32XX_USB_CLK_I2C>; #address-cells = <1>; #size-cells = <0>; @@ -124,7 +128,7 @@ clcd: clcd@31040000 { compatible = "arm,pl110", "arm,primecell"; reg = <0x31040000 0x1000>; - interrupts = <0x0e 0>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_LCD>; clock-names = "apb_pclk"; status = "disabled"; @@ -133,7 +137,7 @@ mac: ethernet@31060000 { compatible = "nxp,lpc-eth"; reg = <0x31060000 0x1000>; - interrupts = <0x1d 0>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_MAC>; }; @@ -161,7 +165,7 @@ ssp0: ssp@20084000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x20084000 0x1000>; - interrupts = <0x14 0>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SSP0>; clock-names = "apb_pclk"; }; @@ -174,7 +178,7 @@ ssp1: ssp@2008c000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x2008c000 0x1000>; - interrupts = <0x15 0>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SSP1>; clock-names = "apb_pclk"; }; @@ -192,7 +196,8 @@ sd: sd@20098000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x20098000 0x1000>; - interrupts = <0x0f 0>, <0x0d 0>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SD>; clock-names = "apb_pclk"; status = "disabled"; @@ -208,7 +213,7 @@ /* actually, ns16550a w/ 64 byte fifos! */ compatible = "nxp,lpc3220-uart"; reg = <0x40090000 0x1000>; - interrupts = <9 0>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; clocks = <&clk LPC32XX_CLK_UART5>; status = "disabled"; @@ -217,7 +222,7 @@ uart3: serial@40080000 { compatible = "nxp,lpc3220-uart"; reg = <0x40080000 0x1000>; - interrupts = <7 0>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; clocks = <&clk LPC32XX_CLK_UART3>; status = "disabled"; @@ -226,7 +231,7 @@ uart4: serial@40088000 { compatible = "nxp,lpc3220-uart"; reg = <0x40088000 0x1000>; - interrupts = <8 0>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; clocks = <&clk LPC32XX_CLK_UART4>; status = "disabled"; @@ -235,7 +240,7 @@ uart6: serial@40098000 { compatible = "nxp,lpc3220-uart"; reg = <0x40098000 0x1000>; - interrupts = <10 0>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; clocks = <&clk LPC32XX_CLK_UART6>; status = "disabled"; @@ -244,7 +249,7 @@ i2c1: i2c@400A0000 { compatible = "nxp,pnx-i2c"; reg = <0x400A0000 0x100>; - interrupts = <0x33 0>; + interrupts = <51 IRQ_TYPE_LEVEL_LOW>; #address-cells = <1>; #size-cells = <0>; pnx,timeout = <0x64>; @@ -254,7 +259,7 @@ i2c2: i2c@400A8000 { compatible = "nxp,pnx-i2c"; reg = <0x400A8000 0x100>; - interrupts = <0x32 0>; + interrupts = <50 IRQ_TYPE_LEVEL_LOW>; #address-cells = <1>; #size-cells = <0>; pnx,timeout = <0x64>; @@ -308,28 +313,28 @@ uart1: serial@40014000 { compatible = "nxp,lpc3220-hsuart"; reg = <0x40014000 0x1000>; - interrupts = <26 0>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; uart2: serial@40018000 { compatible = "nxp,lpc3220-hsuart"; reg = <0x40018000 0x1000>; - interrupts = <25 0>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; uart7: serial@4001c000 { compatible = "nxp,lpc3220-hsuart"; reg = <0x4001c000 0x1000>; - interrupts = <24 0>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; rtc: rtc@40024000 { compatible = "nxp,lpc3220-rtc"; reg = <0x40024000 0x1000>; - interrupts = <0x34 0>; + interrupts = <52 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_RTC>; }; @@ -343,7 +348,7 @@ timer4: timer@4002C000 { compatible = "nxp,lpc3220-timer"; reg = <0x4002C000 0x1000>; - interrupts = <0x3 0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk LPC32XX_CLK_TIMER4>; clock-names = "timerclk"; status = "disabled"; @@ -352,7 +357,7 @@ timer5: timer@40030000 { compatible = "nxp,lpc3220-timer"; reg = <0x40030000 0x1000>; - interrupts = <0x4 0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk LPC32XX_CLK_TIMER5>; clock-names = "timerclk"; status = "disabled"; @@ -369,7 +374,7 @@ reg = <0x40044000 0x1000>; clocks = <&clk LPC32XX_CLK_TIMER0>; clock-names = "timerclk"; - interrupts = <0x10 0>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; }; /* @@ -382,7 +387,7 @@ adc: adc@40048000 { compatible = "nxp,lpc3220-adc"; reg = <0x40048000 0x1000>; - interrupts = <0x27 0>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_ADC>; status = "disabled"; }; @@ -390,7 +395,7 @@ tsc: tsc@40048000 { compatible = "nxp,lpc3220-tsc"; reg = <0x40048000 0x1000>; - interrupts = <0x27 0>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_ADC>; status = "disabled"; }; @@ -398,7 +403,7 @@ timer1: timer@4004C000 { compatible = "nxp,lpc3220-timer"; reg = <0x4004C000 0x1000>; - interrupts = <0x11 0>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk LPC32XX_CLK_TIMER1>; clock-names = "timerclk"; }; @@ -406,14 +411,14 @@ key: key@40050000 { compatible = "nxp,lpc3220-key"; reg = <0x40050000 0x1000>; - interrupts = <54 0>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; timer2: timer@40058000 { compatible = "nxp,lpc3220-timer"; reg = <0x40058000 0x1000>; - interrupts = <0x12 0>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk LPC32XX_CLK_TIMER2>; clock-names = "timerclk"; status = "disabled"; @@ -436,7 +441,7 @@ timer3: timer@40060000 { compatible = "nxp,lpc3220-timer"; reg = <0x40060000 0x1000>; - interrupts = <0x13 0>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk LPC32XX_CLK_TIMER3>; clock-names = "timerclk"; status = "disabled"; From f6d44349165e0c9ce7fd50301683ad32b0f01841 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 21 Dec 2015 21:54:25 +0200 Subject: [PATCH 8/9] arm: dts: phy3250: add lcd and backlight fixed regulators Phytec PHY3250 board has GPIO controlled regulators for LCD and backlight, add their descriptions to board DTS file. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/phy3250.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts index 7d253bb6265a..8ac368f48eda 100644 --- a/arch/arm/boot/dts/phy3250.dts +++ b/arch/arm/boot/dts/phy3250.dts @@ -25,6 +25,28 @@ reg = <0x80000000 0x4000000>; }; + regulators { + backlight_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "backlight_reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio 5 4 0>; + enable-active-high; + regulator-boot-on; + }; + + lcd_reg: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "lcd_reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio 5 0 0>; + enable-active-high; + regulator-boot-on; + }; + }; + ahb { mac: ethernet@31060000 { phy-mode = "rmii"; From d06670e96267d1f1a771f71f5719c0a2c0092ec1 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 21 Dec 2015 21:54:26 +0200 Subject: [PATCH 9/9] arm: dts: phy3250: add SD fixed regulator The change adds fixed voltage regulator for SD controller, ARM MMCI controller driver uses it to control card power management. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/phy3250.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts index 8ac368f48eda..a00d7ce7802b 100644 --- a/arch/arm/boot/dts/phy3250.dts +++ b/arch/arm/boot/dts/phy3250.dts @@ -45,6 +45,15 @@ enable-active-high; regulator-boot-on; }; + + sd_reg: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "sd_reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio 5 5 0>; + enable-active-high; + }; }; ahb { @@ -162,6 +171,7 @@ cd-gpios = <&gpio 3 1 0>; cd-inverted; bus-width = <4>; + vmmc-supply = <&sd_reg>; status = "okay"; }; };