diff --git a/arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts b/arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts
index 2abe261bb09e..d67113558abf 100644
--- a/arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts
+++ b/arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts
@@ -1444,10 +1444,10 @@
 			 "MMC_CAP_HW_RESET",
 			 "MMC_CAP_ERASE",
 			 "MMC_CAP_CMD23";
-		/*caps2 = "MMC_CAP2_HS200";*/
+		caps2 = "MMC_CAP2_HS200";
 		/* "MMC_CAP2_HS400";*/
 		f_min = <400000>;
-		f_max = <50000000>;
+		f_max = <200000000>;
 	};
 };
 
diff --git a/arch/arm64/boot/dts/amlogic/sm1_s905d3_skt.dts b/arch/arm64/boot/dts/amlogic/sm1_s905d3_skt.dts
index ef75f873c773..91af75774434 100644
--- a/arch/arm64/boot/dts/amlogic/sm1_s905d3_skt.dts
+++ b/arch/arm64/boot/dts/amlogic/sm1_s905d3_skt.dts
@@ -1443,10 +1443,10 @@
 			 "MMC_CAP_HW_RESET",
 			 "MMC_CAP_ERASE",
 			 "MMC_CAP_CMD23";
-		/*caps2 = "MMC_CAP2_HS200";*/
+		caps2 = "MMC_CAP2_HS200";
 		/* "MMC_CAP2_HS400";*/
 		f_min = <400000>;
-		f_max = <50000000>;
+		f_max = <200000000>;
 	};
 };
 
diff --git a/drivers/amlogic/mmc/aml_sd_emmc.c b/drivers/amlogic/mmc/aml_sd_emmc.c
index 3196af5a8088..ad3cbbd2d6e3 100644
--- a/drivers/amlogic/mmc/aml_sd_emmc.c
+++ b/drivers/amlogic/mmc/aml_sd_emmc.c
@@ -3659,7 +3659,7 @@ static struct meson_mmc_data mmc_data_sm1 = {
 	.sdmmc.hs.core_phase = 3,
 	.sdmmc.ddr.core_phase = 2,
 	.sdmmc.ddr.tx_phase = 0,
-	.sdmmc.hs2.core_phase = 3,
+	.sdmmc.hs2.core_phase = 2,
 	.sdmmc.hs2.tx_phase = 0,
 	.sdmmc.hs4.tx_delay = 0,
 	.sdmmc.sd_hs.core_phase = 3,
diff --git a/drivers/amlogic/mmc/aml_sd_emmc_v3.c b/drivers/amlogic/mmc/aml_sd_emmc_v3.c
index 888e2c4272c7..0f02a26407f3 100644
--- a/drivers/amlogic/mmc/aml_sd_emmc_v3.c
+++ b/drivers/amlogic/mmc/aml_sd_emmc_v3.c
@@ -1192,8 +1192,10 @@ tunning:
 		nmatch = aml_sd_emmc_tuning_transfer(mmc, opcode,
 				blk_pattern, host->blk_test, blksz);
 		if (nmatch != TUNING_NUM_PER_POINT) {
-			clkc->core_phase = para->hs2.tx_phase;
-			clkc->tx_phase = para->hs2.core_phase;
+			if (host->data->chip_type != MMC_CHIP_SM1) {
+				clkc->core_phase = para->hs2.tx_phase;
+				clkc->tx_phase = para->hs2.core_phase;
+			}
 			writel(vclk, host->base + SD_EMMC_CLOCK_V3);
 			pr_info("%s:try clock:0x%x>>>rx_tuning[%d] = %d\n",
 				mmc_hostname(host->mmc),