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vlock: log level less than 3, enc mode not work properly [1/1]
PD#TV-10211 Problem: log level less than 3, the function call flow changed, and enc mode vlock max line, max pixel varible havn't be initialed. Solution: move initial max line/pixel varible in vlock initial function. Verify: tl1 Change-Id: Ib36662045e28a911bf1585bf57bc849b1952d6f9 Signed-off-by: Yong Qin <yong.qin@amlogic.com>
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@@ -81,7 +81,7 @@ static unsigned int pre_input_freq;
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static unsigned int pre_output_freq;
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static unsigned int vlock_dis_cnt;
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static bool vlock_vmode_changed;
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static unsigned int vlock_notify_event;
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static unsigned int vlock_notify_event = VOUT_EVENT_MODE_CHANGE;
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static unsigned int pre_hiu_reg_m;
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static unsigned int pre_hiu_reg_frac;
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static signed int pre_enc_max_line;
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@@ -511,6 +511,8 @@ static void vlock_setting(struct vframe_s *vf,
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WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
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input_hz, 16, 8);
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temp_value = READ_VPP_REG(enc_max_line_addr);
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if (!temp_value)
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pr_info("vlock err: enc_max_line %d\n", temp_value);
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WRITE_VPP_REG_BITS(VPU_VLOCK_OROW_OCOL_MAX,
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temp_value + 1, 0, 14);
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@@ -686,8 +688,8 @@ void vlock_vmode_check(void)
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const struct vinfo_s *vinfo;
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/*unsigned int t0, t1;*/
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if (vlock_en == 0)
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return;
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/*if (vlock_en == 0)*/
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/* return;*/
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vinfo = get_current_vinfo();
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vlock_vmode_changed = 0;
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@@ -760,6 +762,9 @@ void vlock_vmode_check(void)
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#endif
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pre_enc_max_line = READ_VPP_REG(enc_max_line_addr);
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pre_enc_max_pixel = READ_VPP_REG(enc_max_pixel_addr);
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if (!pre_enc_max_line || !pre_enc_max_pixel)
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pr_info("vlock chk err: maxLine %d,maxPixel %d\n",
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pre_enc_max_line, pre_enc_max_pixel);
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vlock_capture_limit =
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((1024*1024*16)*vlock_line_limit) /
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(vinfo->vtotal + 1);
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@@ -1022,6 +1027,13 @@ static void vlock_enable_step3_enc(void)
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{
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unsigned int line_num = 0, enc_max_line = 0, polity_line_num = 0;
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unsigned int pixel_num = 0, enc_max_pixel = 0, polity_pixel_num = 0;
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unsigned int val;
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if (!pre_enc_max_pixel || !pre_enc_max_line) {
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pr_info("vlock enc max val err P:%d L:%d\n",
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pre_enc_max_pixel, pre_enc_max_line);
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return;
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}
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/*vlock pixel num adjust*/
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if (!(vlock_debug & VLOCK_DEBUG_ENC_PIXEL_ADJ_DIS)) {
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@@ -1034,12 +1046,21 @@ static void vlock_enable_step3_enc(void)
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} else {
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enc_max_pixel = pre_enc_max_pixel + pixel_num;
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}
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if (enc_max_pixel > 0x1fff)
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if (enc_max_pixel > 0x1fff) {
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WRITE_VPP_REG_BITS(enc_max_line_switch_addr,
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pixel_num, 0, 13);
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else
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val = pixel_num;
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} else {
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WRITE_VPP_REG_BITS(enc_max_line_switch_addr,
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enc_max_pixel, 0, 13);
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val = enc_max_pixel;
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}
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if (vlock_debug & VLOCK_DEBUG_INFO) {
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pr_info("pixel:polity_pixel_num=%d, pixel_num=%d, maxP=%d\n",
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polity_pixel_num, pixel_num, pre_enc_max_pixel);
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pr_info("pixel:wr addr:0x%x, 0x%x\n",
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enc_max_line_switch_addr, val);
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}
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}
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/*vlock line num adjust*/
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if (!(vlock_debug & VLOCK_DEBUG_ENC_LINE_ADJ_DIS)) {
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@@ -1055,6 +1076,12 @@ static void vlock_enable_step3_enc(void)
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if (enc_max_pixel > 0x1fff)
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enc_max_line += 1;
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WRITE_VPP_REG(enc_max_line_addr, enc_max_line);
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if (vlock_debug & VLOCK_DEBUG_INFO) {
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pr_info("line:polity_line_num=%d line_num=%d, maxL=%d\n",
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polity_pixel_num, line_num, pre_enc_max_line);
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pr_info("line:wr addr:0x%x, 0x%x\n",
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enc_max_line_addr, enc_max_line);
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}
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}
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if (vlock_log_en && (vlock_log_cnt < vlock_log_size)) {
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@@ -1065,8 +1092,8 @@ static void vlock_enable_step3_enc(void)
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vlock_reg_get();
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vlock_log_cnt++;
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}
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if (vlock_debug & VLOCK_DEBUG_INFO)
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pr_info(">>>[%s]\n", __func__);
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/*if (vlock_debug & VLOCK_DEBUG_INFO)*/
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/* pr_info(">>>[%s]\n", __func__);*/
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}
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static void vlock_enable_step3_soft_enc(void)
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@@ -1730,7 +1757,11 @@ void vlock_status_init(void)
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/*back up orignal pll value*/
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vlock.val_m = vlock_get_panel_pll_m();
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vlock.val_frac = vlock_get_panel_pll_frac();
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/*enc mode initial val*/
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pre_enc_max_line = READ_VPP_REG(enc_max_line_addr);
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pre_enc_max_pixel = READ_VPP_REG(enc_max_pixel_addr);
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pr_info("vlock: maxLine %d,maxPixel %d\n",
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pre_enc_max_line, pre_enc_max_pixel);
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vlock.fsm_sts = VLOCK_STATE_NULL;
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vlock.fsm_prests = VLOCK_STATE_NULL;
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vlock.vf_sts = false;
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@@ -2445,13 +2476,13 @@ void vlock_status(void)
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pr_info("vlock_sync_limit_flag:%d\n", vlock_sync_limit_flag);
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pr_info("pre_hiu_reg_m:0x%x\n", pre_hiu_reg_m);
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pr_info("pre_hiu_reg_frac:0x%x\n", pre_hiu_reg_frac);
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pr_info("pre_enc_max_line:0x%x\n", pre_enc_max_line);
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pr_info("pre_enc_max_pixel:0x%x\n", pre_enc_max_pixel);
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pr_info("enc_max_line_addr:0x%x 0x%x\n",
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enc_max_line_addr, pre_enc_max_line);
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pr_info("enc_max_pixel_addr:0x%x 0x%x\n",
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enc_max_pixel_addr, pre_enc_max_pixel);
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pr_info("vlock_dis_cnt:%d\n", vlock_dis_cnt);
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pr_info("vlock_dis_cnt_no_vf:%d\n", vlock_dis_cnt_no_vf);
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pr_info("vlock_dis_cnt_no_vf_limit:%d\n", vlock_dis_cnt_no_vf_limit);
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pr_info("enc_max_line_addr:0x%x\n", enc_max_line_addr);
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pr_info("enc_max_pixel_addr:0x%x\n", enc_max_pixel_addr);
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pr_info("enc_video_mode_addr:0x%x\n", enc_video_mode_addr);
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pr_info("enc_max_line_switch_addr:0x%x\n", enc_max_line_switch_addr);
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pr_info("vlock_capture_limit:0x%x\n", vlock_capture_limit);
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@@ -2509,6 +2540,10 @@ void vlock_reg_dump(void)
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pr_info("[0x1cb3]=0x%08x\n", READ_VPP_REG(0x1cb3));
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pr_info("[0x1cb4]=0x%08x\n", READ_VPP_REG(0x1cb4));
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pr_info("[0x1cc8]=0x%08x\n", READ_VPP_REG(0x1cc8));
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pr_info("[0x%x]=0x%08x\n", enc_max_line_addr,
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READ_VPP_REG(enc_max_line_addr));
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pr_info("[0x%x]=0x%08x\n", enc_max_pixel_addr,
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READ_VPP_REG(enc_max_pixel_addr));
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/*amvecm_hiu_reg_read(hhi_pll_reg_m, &val);*/
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val = vlock_get_panel_pll_m();
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@@ -2525,6 +2560,7 @@ void vlock_reg_dump(void)
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pr_info("HIU HDMI_PLL_CNTL2 0x%x=0x%x\n",
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HHI_HDMI_PLL_CNTL2, val);
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}
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/*back up orignal pll value*/
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/*pr_info("HIU pll m[0x%x]=0x%x\n", hhi_pll_reg_m, vlock.val_m);*/
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/*pr_info("HIU pll f[0x%x]=0x%x\n", hhi_pll_reg_frac, vlock.val_frac);*/
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@@ -2652,7 +2688,7 @@ int vlock_notify_callback(struct notifier_block *block, unsigned long cmd,
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return -1;
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}
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if (vlock_debug & VLOCK_DEBUG_INFO)
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pr_info("current vmode=%s, vinfo w=%d,h=%d, cmd: 0x%lx\n",
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pr_info("vlock notify vmode=%s, vinfo w=%d,h=%d, cmd: 0x%lx\n",
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vinfo->name, vinfo->width, vinfo->height, cmd);
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switch (cmd) {
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@@ -23,7 +23,7 @@
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#include <linux/amlogic/media/vfm/vframe.h>
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#include "linux/amlogic/media/amvecm/ve.h"
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#define VLOCK_VER "Ref.2019/8/18:vlock for double frq out"
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#define VLOCK_VER "Ref.2019/9/17:log level 3 enc mode not work properly"
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#define VLOCK_REG_NUM 33
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