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scsi: ufs: ufs-qcom: Clear qunipro_g4_sel for HW version major 5
[ Upstream commit 9c02aa24bf ]
On SM8550, depending on the Qunipro, we can run with G5 or G4. For now,
when the major version is 5 or above, we go with G5. Therefore, we need to
specifically tell UFS HC that.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Stable-dep-of: 823150ecf04f ("scsi: ufs: qcom: Perform read back after writing unipro mode")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
1e33175a8c
commit
9c4e9090af
@@ -226,6 +226,10 @@ static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
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ufshcd_rmwl(host->hba, QUNIPRO_SEL,
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ufshcd_rmwl(host->hba, QUNIPRO_SEL,
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ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
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ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
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REG_UFS_CFG1);
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REG_UFS_CFG1);
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if (host->hw_ver.major == 0x05)
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ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0);
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/* make sure above configuration is applied before we return */
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/* make sure above configuration is applied before we return */
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mb();
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mb();
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}
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}
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@@ -498,9 +502,9 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
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mb();
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mb();
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}
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}
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if (update_link_startup_timer) {
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if (update_link_startup_timer && host->hw_ver.major != 0x5) {
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ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
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ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
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REG_UFS_PA_LINK_STARTUP_TIMER);
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REG_UFS_CFG0);
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/*
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/*
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* make sure that this configuration is applied before
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* make sure that this configuration is applied before
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* we return
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* we return
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@@ -38,7 +38,8 @@ enum {
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REG_UFS_PA_ERR_CODE = 0xCC,
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REG_UFS_PA_ERR_CODE = 0xCC,
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/* On older UFS revisions, this register is called "RETRY_TIMER_REG" */
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/* On older UFS revisions, this register is called "RETRY_TIMER_REG" */
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REG_UFS_PARAM0 = 0xD0,
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REG_UFS_PARAM0 = 0xD0,
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REG_UFS_PA_LINK_STARTUP_TIMER = 0xD8,
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/* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */
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REG_UFS_CFG0 = 0xD8,
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REG_UFS_CFG1 = 0xDC,
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REG_UFS_CFG1 = 0xDC,
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REG_UFS_CFG2 = 0xE0,
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REG_UFS_CFG2 = 0xE0,
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REG_UFS_HW_VERSION = 0xE4,
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REG_UFS_HW_VERSION = 0xE4,
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@@ -76,6 +77,9 @@ enum {
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#define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x)
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#define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x)
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#define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x)
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#define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x)
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/* bit definitions for REG_UFS_CFG0 register */
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#define QUNIPRO_G4_SEL BIT(5)
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/* bit definitions for REG_UFS_CFG1 register */
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/* bit definitions for REG_UFS_CFG1 register */
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#define QUNIPRO_SEL 0x1
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#define QUNIPRO_SEL 0x1
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#define UTP_DBG_RAMS_EN 0x20000
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#define UTP_DBG_RAMS_EN 0x20000
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