From 9c7320f1234d638027f86c242cee1ad73f1b1ec3 Mon Sep 17 00:00:00 2001
From: Ziyuan Xu <xzy.xu@rock-chips.com>
Date: Mon, 25 Apr 2022 09:28:14 +0800
Subject: [PATCH] ARM: dts: rockchip: rv1106g-evb2: change sfc_max_freq to
 125MHz

The parent clock of sclk_sfc are 500m_300m_200m_24m, so that can't set
sclk_sfc to 118.8MHz.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I71b60000a465c23e88155ac9da95cf046717a6d8
---
 arch/arm/boot/dts/rv1106g-evb2-v10.dts | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/rv1106g-evb2-v10.dts b/arch/arm/boot/dts/rv1106g-evb2-v10.dts
index 5eb2656e013a..622190aa2fbd 100644
--- a/arch/arm/boot/dts/rv1106g-evb2-v10.dts
+++ b/arch/arm/boot/dts/rv1106g-evb2-v10.dts
@@ -231,12 +231,14 @@
 };
 
 &sfc {
+	assigned-clocks = <&cru SCLK_SFC>;
+	assigned-clock-rates = <125000000>;
 	status = "okay";
 
 	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
-		spi-max-frequency = <118800000>;
+		spi-max-frequency = <125000000>;
 		spi-rx-bus-width = <4>;
 		spi-tx-bus-width = <1>;
 	};