From 9dc5ea55438f00790c1f46da8890ec5797b443da Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 2 Dec 2020 17:10:29 +0800 Subject: [PATCH] phy: rockchip: naneng-combphy: Fix support for pipe clock settings pipe clock settings were done before PCIe's and SATA's catch-all pipe settings. So it would be covered by con1_for_pcie and con1_for_sata. Fix this by moving pipe clock settings to the end. Change-Id: I19a8943b6a99d8e4ef198345ec3f62bdac491c58 Signed-off-by: Shawn Lin --- .../rockchip/phy-rockchip-naneng-combphy.c | 56 +++++++++---------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 61f1516e5d0e..6e81e6c47d37 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -320,34 +320,6 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) return -EINVAL; } - rate = clk_get_rate(refclk); - - switch (rate) { - case 24000000: - if (priv->mode == PHY_TYPE_USB3) { - /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ - val = readl(priv->mmio + (0x0e << 2)); - val &= ~GENMASK(7, 6); - val |= 0x01 << 6; - writel(val, priv->mmio + (0x0e << 2)); - - val = readl(priv->mmio + (0x0f << 2)); - val &= ~GENMASK(7, 0); - val |= 0x5f; - writel(val, priv->mmio + (0x0f << 2)); - } - break; - case 25000000: - param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); - break; - case 100000000: - param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); - break; - default: - dev_err(priv->dev, "Unsupported rate: %lu\n", rate); - return -EINVAL; - } - switch (priv->mode) { case PHY_TYPE_PCIE: param_write(priv->phy_grf, &cfg->con0_for_pcie, true); @@ -397,6 +369,34 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) return -EINVAL; } + rate = clk_get_rate(refclk); + + switch (rate) { + case 24000000: + if (priv->mode == PHY_TYPE_USB3) { + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ + val = readl(priv->mmio + (0x0e << 2)); + val &= ~GENMASK(7, 6); + val |= 0x01 << 6; + writel(val, priv->mmio + (0x0e << 2)); + + val = readl(priv->mmio + (0x0f << 2)); + val &= ~GENMASK(7, 0); + val |= 0x5f; + writel(val, priv->mmio + (0x0f << 2)); + } + break; + case 25000000: + param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); + break; + case 100000000: + param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + break; + default: + dev_err(priv->dev, "Unsupported rate: %lu\n", rate); + return -EINVAL; + } + return 0; }