diff --git a/drivers/clk/rockchip/clk-rv1126.c b/drivers/clk/rockchip/clk-rv1126.c
index 9432f1e87380..65f1e32001ab 100644
--- a/drivers/clk/rockchip/clk-rv1126.c
+++ b/drivers/clk/rockchip/clk-rv1126.c
@@ -681,6 +681,9 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
 	COMPOSITE(CLK_CAN, "clk_can", mux_gpll_xin24m_p, 0,
 			RV1126_CLKSEL_CON(25), 1, 1, MFLAGS, 0, 7, DFLAGS,
 			RV1126_CLKGATE_CON(7), 9, GFLAGS),
+	/* pclk_otp and clk_otp are controlled by sgrf_clkgat_con. */
+	SGRF_GATE(CLK_OTP, "clk_otp", "xin24m"),
+	SGRF_GATE(PCLK_OTP, "pclk_otp", "pclk_pdbus"),
 
 	GATE(PCLK_NPU_TSADC, "pclk_npu_tsadc", "pclk_pdbus", 0,
 			RV1126_CLKGATE_CON(24), 3, GFLAGS),
diff --git a/include/dt-bindings/clock/rv1126-cru.h b/include/dt-bindings/clock/rv1126-cru.h
index cc725ec9f7a6..291155a9a866 100644
--- a/include/dt-bindings/clock/rv1126-cru.h
+++ b/include/dt-bindings/clock/rv1126-cru.h
@@ -211,6 +211,7 @@
 #define CLK_CORE_NPUPVTM	145
 #define CLK_NPUPVTM		146
 #define SCLK_DDRCLK		147
+#define CLK_OTP			148
 
 /* dclk */
 #define DCLK_DECOM		150
@@ -351,8 +352,9 @@
 #define PCLK_CSIPHY1		291
 #define PCLK_USBPHY_HOST	292
 #define PCLK_USBPHY_OTG		293
+#define PCLK_OTP		294
 
-#define CLK_NR_CLKS		(PCLK_USBPHY_OTG + 1)
+#define CLK_NR_CLKS		(PCLK_OTP + 1)
 
 /* pmu soft-reset indices */