From 9ebe4c4202c5972f0110ecb616c8670a0bd15ed4 Mon Sep 17 00:00:00 2001
From: Elaine Zhang <zhangqing@rock-chips.com>
Date: Tue, 12 Nov 2024 16:48:43 +0800
Subject: [PATCH] arm64: dts: rockchip: rv1126b: add can dts nodes

Change-Id: I96089a83a67e0c0c06bb83745ee4079e5c105d33
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rv1126b.dtsi | 26 +++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
index 952ddc0e5f1b..1c6fff7913af 100644
--- a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
@@ -228,6 +228,32 @@
 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
+	can0: can@21d40000 {
+		compatible = "rockchip,rv1126b-canfd";
+		reg = <0x21d40000 0x1000>;
+		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_CAN0>, <&cru HCLK_CAN0>;
+		clock-names = "baudclk", "apb_pclk";
+		resets = <&cru SRST_RESETN_CAN0>, <&cru SRST_HRESETN_CAN0>;
+		reset-names = "can", "can-apb";
+		dmas = <&dmac 44>;
+		dma-names = "rx";
+		status = "disabled";
+	};
+
+	can1: can@21d50000 {
+		compatible = "rockchip,rv1126b-canfd";
+		reg = <0x21d50000 0x1000>;
+		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_CAN1>, <&cru HCLK_CAN1>;
+		clock-names = "baudclk", "apb_pclk";
+		resets = <&cru SRST_RESETN_CAN1>, <&cru SRST_HRESETN_CAN1>;
+		reset-names = "can", "can-apb";
+		dmas = <&dmac 45>;
+		dma-names = "rx";
+		status = "disabled";
+	};
+
 	hw_decompress: decompress@22100000 {
 		compatible = "rockchip,hw-decompress";
 		reg = <0x22100000 0x1000>;