From 9f8075b8ae575eef7b784125adfd1c8ec540dd85 Mon Sep 17 00:00:00 2001 From: YouMin Chen Date: Thu, 16 Jun 2022 10:06:45 +0800 Subject: [PATCH] PM / devfreq: rockchip_dmc: clear the irq if waiting complt_irq timeout If waiting for wait_ctrl.complt_irq times out, clear the IRQ and stop the MCU by sip_smc_dram(DRAM_POST_SET_RATE). Prevent the complt_irq which blocked from responding in the next DDR frequency conversion flow. Signed-off-by: YouMin Chen Change-Id: I771ac2471dd1ef388f249c367d4f875ea0502e6c --- drivers/devfreq/rockchip_dmc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/devfreq/rockchip_dmc.c b/drivers/devfreq/rockchip_dmc.c index 1bd2f8ba1e43..84ab49f76521 100644 --- a/drivers/devfreq/rockchip_dmc.c +++ b/drivers/devfreq/rockchip_dmc.c @@ -1207,6 +1207,16 @@ int rockchip_dmcfreq_wait_complete(void) wait_event_timeout(wait_ctrl.wait_wq, (wait_ctrl.wait_flag == 0), msecs_to_jiffies(wait_ctrl.wait_time_out_ms)); + /* + * If waiting for wait_ctrl.complt_irq times out, clear the IRQ and stop the MCU by + * sip_smc_dram(DRAM_POST_SET_RATE). + */ + if (wait_ctrl.dcf_en == 2 && wait_ctrl.wait_flag != 0) { + res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_POST_SET_RATE); + if (res.a0) + pr_err("%s: dram post set rate error:%lx\n", __func__, res.a0); + } + cpu_latency_qos_update_request(&pm_qos, PM_QOS_DEFAULT_VALUE); disable_irq(wait_ctrl.complt_irq);