From a19f9979e4b29d8dc9919f387ca62c8d72e4bf80 Mon Sep 17 00:00:00 2001 From: David Wu Date: Fri, 28 Apr 2017 17:33:24 +0800 Subject: [PATCH] ethernet: stmmac: rockchip: Fix the correct clock for mdc divider The MDC clock is divider from APB Clock for rockchip's socs, if it was from mac_clk, the mdc clk range might not be between the frequency range 1.0 MHz - 2.5 MHz. Change-Id: I4e4fcb1be239a8d78a39fc1f4e2af5bb87258798 Signed-off-by: David Wu --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index b44833580ca1..50320adeb474 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -206,7 +206,7 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv) { u32 clk_rate; - clk_rate = clk_get_rate(priv->plat->stmmac_clk); + clk_rate = clk_get_rate(priv->plat->pclk); /* Platform provided default clk_csr would be assumed valid * for all other cases except for the below mentioned ones. diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index af34a4cadbb0..3a673d48846b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -576,7 +576,7 @@ stmmac_probe_config_dt(struct platform_device *pdev, const char **mac) clk_prepare_enable(plat->stmmac_clk); } - plat->pclk = devm_clk_get(&pdev->dev, "pclk"); + plat->pclk = devm_clk_get(&pdev->dev, "pclk_mac"); if (IS_ERR(plat->pclk)) { if (PTR_ERR(plat->pclk) == -EPROBE_DEFER) goto error_pclk_get;