From a1a02755f2da4a14d3874830f5c28d74de26959d Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Fri, 4 Nov 2022 01:32:39 +0000 Subject: [PATCH] clk: rockchip: pll: Add ROCKCHIP_PLL_FIXED_MODE for pll_rk3036/rk3328 type PLL can be normal mode only. Signed-off-by: Joseph Chen Change-Id: I331e107b561047aa6b46a6c2f7df539a77a6da2d --- drivers/clk/rockchip/clk-pll.c | 10 ++++++---- drivers/clk/rockchip/clk.h | 5 +++++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 35b0badde76a..b076568cb377 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -578,10 +578,12 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, rockchip_rk3036_pll_get_params(pll, &cur); cur.rate = 0; - cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); - if (cur_parent == PLL_MODE_NORM) { - pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); - rate_change_remuxed = 1; + if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) { + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); + if (cur_parent == PLL_MODE_NORM) { + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); + rate_change_remuxed = 1; + } } /* update pll values */ diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 448634d86c1f..1a14aea0e61b 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -505,7 +505,12 @@ struct rockchip_pll_clock { struct rockchip_pll_rate_table *rate_table; }; +/* + * PLL flags + */ #define ROCKCHIP_PLL_SYNC_RATE BIT(0) +/* normal mode only. now only for pll_rk3036, pll_rk3328 type */ +#define ROCKCHIP_PLL_FIXED_MODE BIT(1) #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ _lshift, _pflags, _rtable) \