From a20520933058421f59ef6345da4e09cc84cf63da Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Tue, 8 Apr 2025 20:21:57 +0800 Subject: [PATCH] drm/bridge: analogix_dp: Add &link_train.max_link_rate and &link_train.max_lane_count The &link_train.link_rate and &link_train.lane_count are used as the max_link_rate and max_lane_count to check the bandwidth limitation , select output format and so on. However, they both also are used as the actual link_rate and lane_count for the eDP controller and phy. So we add &link_train.max_link_rate and &link_train.max_lane_count in order to avoid the confusion in the use of above variables. On the other hand, some unexpected errors will occur without this patch in some cases. When I test the PSR function of eDP panel module NE160QAM-NX1, the link rate will be set to the 8.1G, which is the max supported link rate of this module, after exiting the PSR state, but it should be 5.4G corresponding to 3840x2400p60 resolution. analogix_dp_detect(): set the &link_train.link_rate to 8.1G -> analogix_dp_fast_link_train(): use the &link_train.link_rate as the previous link config -> analogix_dp_set_link_bandwidth() -> phy_configure(): error: invalid link_rate config 8.1G Change-Id: I1a4ae3c1eb308c9e0d25fb7736de52336ea7f880 Signed-off-by: Damon Ding --- drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 14 +++++++------- drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 2 ++ 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index 88e2a5a8f022..c37201c4fb78 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -783,7 +783,7 @@ static int analogix_dp_select_rx_bandwidth(struct analogix_dp_device *dp) * Select the smaller one between rx DP_MAX_LINK_RATE * and the max link rate supported by the platform. */ - dp->link_train.link_rate = min_t(u32, dp->link_train.link_rate, + dp->link_train.link_rate = min_t(u32, dp->link_train.max_link_rate, dp->video_info.max_link_rate); if (!dp->link_train.link_rate) return -EINVAL; @@ -1589,13 +1589,13 @@ analogix_dp_detect(struct analogix_dp_device *dp) if (!analogix_dp_detect_hpd(dp)) { /* Initialize by reading RX's DPCD */ - ret = analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); + ret = analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.max_link_rate); if (ret) { dev_err(dp->dev, "failed to read max link rate\n"); goto out; } - ret = analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); + ret = analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.max_lane_count); if (ret) { dev_err(dp->dev, "failed to read max lane count\n"); goto out; @@ -2159,9 +2159,9 @@ analogix_dp_bridge_mode_valid(struct drm_bridge *bridge, min_bpp = 24; max_link_rate = min_t(u32, dp->video_info.max_link_rate, - dp->link_train.link_rate); + dp->link_train.max_link_rate); max_lane_count = min_t(u32, dp->video_info.max_lane_count, - dp->link_train.lane_count); + dp->link_train.max_lane_count); if (analogix_dp_link_config_validate(max_link_rate, max_lane_count) && !analogix_dp_bandwidth_ok(dp, &m, min_bpp, drm_dp_bw_code_to_link_rate(max_link_rate), @@ -2214,8 +2214,8 @@ static u32 *analogix_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bri if (!analogix_dp_bandwidth_ok(dp, &crtc_state->mode, analogix_dp_get_output_bpp(fmt), - drm_dp_bw_code_to_link_rate(dp->link_train.link_rate), - dp->link_train.lane_count)) + drm_dp_bw_code_to_link_rate(dp->link_train.max_link_rate), + dp->link_train.max_lane_count)) continue; output_fmts[j++] = fmt->bus_format; diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h index 8b1da11064bd..879a56eab2b7 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h @@ -158,6 +158,8 @@ struct link_train { u8 link_rate; u8 lane_count; u8 training_lane[4]; + u8 max_link_rate; + u8 max_lane_count; bool ssc; bool enhanced_framing; bool assr;