shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-09 20:32:04 +09:00
Code Issues Packages Projects Releases Wiki Activity

clk: add protection mechanism for all plls [1/1]

Browse Source 
PD#SWPL-14024

Problem:
add protection mechanism for all plls

Solution:
add protection mechanism for all plls

Verify:
test passed on
1)axg
2)g12a
3)txl
4)txlx

Change-Id: I6f29026422f73c690854d5ffa292857d14922d22
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
This commit is contained in:
Jian Hu
2019-09-11 14:05:35 +08:00
committed by Tao Zeng
parent 1096d6b1bf
commit a29df37e41
3 changed files with 210 additions and 186 deletions
Download Patch File Download Diff File Expand all files Collapse all files

100
drivers/amlogic/clk/axg/axg_clk-pll.c
View File

@@ -176,7 +176,7 @@ static int meson_axg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
const struct pll_rate_table *rate_set;
unsigned long old_rate;
unsigned int tmp;
int ret = 0;
int ret = 0, j = 10;
u32 reg;
unsigned long flags = 0;
@@ -206,54 +206,62 @@ static int meson_axg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
}
}
if (!strcmp(clk_hw_get_name(hw), "gp0_pll")
|| !strcmp(clk_hw_get_name(hw), "hifi_pll")
|| !strcmp(clk_hw_get_name(hw), "pcie_pll")) {
do {
void *cntlbase = pll->base + p->reg_off;
if (!strcmp(clk_hw_get_name(hw), "gp0_pll") ||
!strcmp(clk_hw_get_name(hw), "hifi_pll") ||
!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
writel(AXG_PCIE_PLL_CNTL,
cntlbase + (unsigned long)(0 * 4));
writel(AXG_PCIE_PLL_CNTL1,
cntlbase + (unsigned long)(1 * 4));
writel(AXG_PCIE_PLL_CNTL2,
cntlbase + (unsigned long)(2 * 4));
writel(AXG_PCIE_PLL_CNTL3,
cntlbase + (unsigned long)(3 * 4));
writel(AXG_PCIE_PLL_CNTL4,
cntlbase + (unsigned long)(4 * 4));
writel(AXG_PCIE_PLL_CNTL5,
cntlbase + (unsigned long)(5 * 4));
writel(AXG_PCIE_PLL_CNTL6,
cntlbase + (unsigned long)(6 * 4));
} else if (!strcmp(clk_hw_get_name(hw), "hifi_pll")) {
writel(AXG_HIFI_PLL_CNTL1,
cntlbase + (unsigned long)(6 * 4));
writel(AXG_HIFI_PLL_CNTL2,
cntlbase + (unsigned long)(1 * 4));
writel(AXG_HIFI_PLL_CNTL3,
cntlbase + (unsigned long)(2 * 4));
writel(AXG_HIFI_PLL_CNTL4,
cntlbase + (unsigned long)(3 * 4));
writel(AXG_HIFI_PLL_CNTL5,
cntlbase + (unsigned long)(4 * 4));
} else {
writel(GXL_GP0_CNTL1,
cntlbase + (unsigned long)(6 * 4));
writel(GXL_GP0_CNTL2,
cntlbase + (unsigned long)(1 * 4));
writel(GXL_GP0_CNTL3,
cntlbase + (unsigned long)(2 * 4));
writel(GXL_GP0_CNTL4,
cntlbase + (unsigned long)(3 * 4));
writel(GXL_GP0_CNTL5,
cntlbase + (unsigned long)(4 * 4));
}
if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
writel(AXG_PCIE_PLL_CNTL,
cntlbase + (unsigned long)(0*4));
writel(AXG_PCIE_PLL_CNTL1,
cntlbase + (unsigned long)(1*4));
writel(AXG_PCIE_PLL_CNTL2,
cntlbase + (unsigned long)(2*4));
writel(AXG_PCIE_PLL_CNTL3,
cntlbase + (unsigned long)(3*4));
writel(AXG_PCIE_PLL_CNTL4,
cntlbase + (unsigned long)(4*4));
writel(AXG_PCIE_PLL_CNTL5,
cntlbase + (unsigned long)(5*4));
writel(AXG_PCIE_PLL_CNTL6,
cntlbase + (unsigned long)(6*4));
} else if (!strcmp(clk_hw_get_name(hw), "hifi_pll")) {
writel(AXG_HIFI_PLL_CNTL1,
cntlbase + (unsigned long)(6*4));
writel(AXG_HIFI_PLL_CNTL2,
cntlbase + (unsigned long)(1*4));
writel(AXG_HIFI_PLL_CNTL3,
cntlbase + (unsigned long)(2*4));
writel(AXG_HIFI_PLL_CNTL4,
cntlbase + (unsigned long)(3*4));
writel(AXG_HIFI_PLL_CNTL5,
cntlbase + (unsigned long)(4*4));
} else {
writel(GXL_GP0_CNTL1,
cntlbase + (unsigned long)(6*4));
writel(GXL_GP0_CNTL2,
cntlbase + (unsigned long)(1*4));
writel(GXL_GP0_CNTL3,
cntlbase + (unsigned long)(2*4));
writel(GXL_GP0_CNTL4,
cntlbase + (unsigned long)(3*4));
writel(GXL_GP0_CNTL5,
cntlbase + (unsigned long)(4*4));
reg = readl(pll->base + p->reg_off);
writel(((reg | (MESON_PLL_ENABLE)) &
(~MESON_PLL_RESET)), pll->base + p->reg_off);
}
reg = readl(pll->base + p->reg_off);
writel(((reg | (MESON_PLL_ENABLE)) &
(~MESON_PLL_RESET)), pll->base + p->reg_off);
}
/* waiting for 50us to check is locked or not */
udelay(50);
/* lock bit is in the cntlbase */
if (readl(cntlbase + (unsigned long)(0 * 4))
& MESON_PLL_LOCK)
break;
j--;
} while (j);
reg = readl(pll->base + p->reg_off);

85
drivers/amlogic/clk/clk-pll.c
View File

@@ -164,7 +164,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
const struct pll_rate_table *rate_set;
unsigned long old_rate;
unsigned int tmp;
int ret = 0;
int ret = 0, j = 10;
u32 reg;
if (parent_rate == 0 || rate == 0)
@@ -178,50 +178,57 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
p = &pll->n;
if (!strcmp(clk_hw_get_name(hw), "gp0_pll")) {
do {
void *cntlbase = pll->base + p->reg_off;
if (!strcmp(clk_hw_get_name(hw), "gp0_pll")) {
if ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXBB) ||
(get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB)) {
writel(GXBB_GP0_CNTL2,
cntlbase + (unsigned long)(1 * 4));
writel(GXBB_GP0_CNTL3,
cntlbase + (unsigned long)(2 * 4));
writel(GXBB_GP0_CNTL4,
cntlbase + (unsigned long)(3 * 4));
} else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) {
writel(GXL_GP0_CNTL1,
cntlbase + (unsigned long)(6 * 4));
writel(GXL_GP0_CNTL2,
cntlbase + (unsigned long)(1 * 4));
writel(GXL_GP0_CNTL3,
cntlbase + (unsigned long)(2 * 4));
writel(GXL_GP0_CNTL4,
cntlbase + (unsigned long)(3 * 4));
writel(GXL_GP0_CNTL5,
cntlbase + (unsigned long)(4 * 4));
if ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXBB) ||
(get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB)) {
writel(GXBB_GP0_CNTL2,
cntlbase + (unsigned long)(1*4));
writel(GXBB_GP0_CNTL3,
cntlbase + (unsigned long)(2*4));
writel(GXBB_GP0_CNTL4,
cntlbase + (unsigned long)(3*4));
} else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) {
writel(GXL_GP0_CNTL1,
cntlbase + (unsigned long)(6*4));
writel(GXL_GP0_CNTL2,
cntlbase + (unsigned long)(1*4));
writel(GXL_GP0_CNTL3,
cntlbase + (unsigned long)(2*4));
writel(GXL_GP0_CNTL4,
cntlbase + (unsigned long)(3*4));
writel(GXL_GP0_CNTL5,
cntlbase + (unsigned long)(4*4));
reg = readl(pll->base + p->reg_off);
writel(((reg | (MESON_PLL_ENABLE)) &
reg = readl(pll->base + p->reg_off);
writel(((reg | (MESON_PLL_ENABLE)) &
(~MESON_PLL_RESET)), pll->base + p->reg_off);
} else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXLX) {
writel(GXL_GP0_CNTL1,
cntlbase + (unsigned long)(6*4));
writel(GXL_GP0_CNTL2,
cntlbase + (unsigned long)(1*4));
writel(GXL_GP0_CNTL3,
cntlbase + (unsigned long)(2*4));
writel(GXL_GP0_CNTL4,
cntlbase + (unsigned long)(3*4));
writel(TXLL_GP0_CNTL5,
cntlbase + (unsigned long)(4*4));
} else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXLX) {
writel(GXL_GP0_CNTL1,
cntlbase + (unsigned long)(6 * 4));
writel(GXL_GP0_CNTL2,
cntlbase + (unsigned long)(1 * 4));
writel(GXL_GP0_CNTL3,
cntlbase + (unsigned long)(2 * 4));
writel(GXL_GP0_CNTL4,
cntlbase + (unsigned long)(3 * 4));
writel(TXLL_GP0_CNTL5,
cntlbase + (unsigned long)(4 * 4));
reg = readl(pll->base + p->reg_off);
writel(((reg | (MESON_PLL_ENABLE)) &
reg = readl(pll->base + p->reg_off);
writel(((reg | (MESON_PLL_ENABLE)) &
(~MESON_PLL_RESET)), pll->base + p->reg_off);
}
}
}
/* waiting for 50us to check is locked or not */
udelay(50);
/* lock bit is in the cntlbase */
if (readl(cntlbase + (unsigned long)(0 * 4))
& MESON_PLL_LOCK)
break;
j--;
} while (j);
reg = readl(pll->base + p->reg_off);

211
drivers/amlogic/clk/g12a/g12a_clk-pll.c
View File

@@ -222,7 +222,7 @@ static int meson_g12a_pll_set_rate(struct clk_hw *hw, unsigned long rate,
const struct pll_rate_table *rate_set;
unsigned long old_rate;
unsigned long tmp;
int ret = 0;
int ret = 0, j = 10;
u32 reg;
unsigned long flags = 0;
void *cntlbase;
@@ -257,106 +257,115 @@ static int meson_g12a_pll_set_rate(struct clk_hw *hw, unsigned long rate,
cntlbase = pll->base + p->reg_off;
if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
writel(G12A_PCIE_PLL_CNTL0_0,
cntlbase + (unsigned long)(0*4));
writel(G12A_PCIE_PLL_CNTL0_1,
cntlbase + (unsigned long)(0*4));
writel(G12A_PCIE_PLL_CNTL1,
cntlbase + (unsigned long)(1*4));
writel(G12A_PCIE_PLL_CNTL2,
cntlbase + (unsigned long)(2*4));
writel(G12A_PCIE_PLL_CNTL3,
cntlbase + (unsigned long)(3*4));
writel(G12A_PCIE_PLL_CNTL4,
cntlbase + (unsigned long)(4*4));
writel(G12A_PCIE_PLL_CNTL5,
cntlbase + (unsigned long)(5*4));
writel(G12A_PCIE_PLL_CNTL5_,
cntlbase + (unsigned long)(5*4));
udelay(20);
writel(G12A_PCIE_PLL_CNTL4_,
cntlbase + (unsigned long)(4*4));
udelay(10);
/*set pcie_apll_afc_start bit*/
writel(G12A_PCIE_PLL_CNTL0_2,
cntlbase + (unsigned long)(0*4));
writel(G12A_PCIE_PLL_CNTL0_3,
cntlbase + (unsigned long)(0*4));
udelay(10);
writel(G12A_PCIE_PLL_CNTL2_,
cntlbase + (unsigned long)(2*4));
goto OUT;
} else if (!strcmp(clk_hw_get_name(hw), "sys_pll")) {
writel((readl(cntlbase) | MESON_PLL_RESET)
& (~MESON_PLL_ENABLE), cntlbase);
writel(G12A_SYS_PLL_CNTL1,
cntlbase + (unsigned long)(1*4));
writel(G12A_SYS_PLL_CNTL2,
cntlbase + (unsigned long)(2*4));
writel(G12A_SYS_PLL_CNTL3,
cntlbase + (unsigned long)(3*4));
writel(G12A_SYS_PLL_CNTL4,
cntlbase + (unsigned long)(4*4));
writel(G12A_SYS_PLL_CNTL5,
cntlbase + (unsigned long)(5*4));
writel(G12A_PLL_CNTL6,
cntlbase + (unsigned long)(6*4));
udelay(10);
} else if (!strcmp(clk_hw_get_name(hw), "sys1_pll")) {
writel((readl(cntlbase) | MESON_PLL_RESET)
& (~MESON_PLL_ENABLE), cntlbase);
writel(G12A_SYS1_PLL_CNTL1,
cntlbase + (unsigned long)(1*4));
writel(G12A_SYS1_PLL_CNTL2,
cntlbase + (unsigned long)(2*4));
writel(G12A_SYS1_PLL_CNTL3,
cntlbase + (unsigned long)(3*4));
writel(G12A_SYS1_PLL_CNTL4,
cntlbase + (unsigned long)(4*4));
writel(G12A_SYS1_PLL_CNTL5,
cntlbase + (unsigned long)(5*4));
writel(G12A_PLL_CNTL6,
cntlbase + (unsigned long)(6*4));
udelay(10);
} else if (!strcmp(clk_hw_get_name(hw), "gp0_pll")
|| !strcmp(clk_hw_get_name(hw), "gp1_pll")) {
writel((readl(cntlbase) | MESON_PLL_RESET)
& (~MESON_PLL_ENABLE), cntlbase);
writel(G12A_GP0_PLL_CNTL1,
cntlbase + (unsigned long)(1*4));
writel(G12A_GP0_PLL_CNTL2,
cntlbase + (unsigned long)(2*4));
writel(G12A_GP0_PLL_CNTL3,
cntlbase + (unsigned long)(3*4));
writel(G12A_GP0_PLL_CNTL4,
cntlbase + (unsigned long)(4*4));
writel(G12A_GP0_PLL_CNTL5,
cntlbase + (unsigned long)(5*4));
writel(G12A_PLL_CNTL6,
cntlbase + (unsigned long)(6*4));
udelay(10);
} else if (!strcmp(clk_hw_get_name(hw), "hifi_pll")) {
writel((readl(cntlbase) | MESON_PLL_RESET)
& (~MESON_PLL_ENABLE), cntlbase);
writel(G12A_HIFI_PLL_CNTL1,
cntlbase + (unsigned long)(1*4));
writel(G12A_HIFI_PLL_CNTL2,
cntlbase + (unsigned long)(2*4));
writel(G12A_HIFI_PLL_CNTL3,
cntlbase + (unsigned long)(3*4));
writel(G12A_HIFI_PLL_CNTL4,
cntlbase + (unsigned long)(4*4));
writel(G12A_HIFI_PLL_CNTL5,
cntlbase + (unsigned long)(5*4));
writel(G12A_PLL_CNTL6,
cntlbase + (unsigned long)(6*4));
udelay(10);
} else {
pr_err("%s: %s pll not found!!!\n",
__func__, clk_hw_get_name(hw));
return -EINVAL;
}
do {
if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
writel(G12A_PCIE_PLL_CNTL0_0,
cntlbase + (unsigned long)(0 * 4));
writel(G12A_PCIE_PLL_CNTL0_1,
cntlbase + (unsigned long)(0 * 4));
writel(G12A_PCIE_PLL_CNTL1,
cntlbase + (unsigned long)(1 * 4));
writel(G12A_PCIE_PLL_CNTL2,
cntlbase + (unsigned long)(2 * 4));
writel(G12A_PCIE_PLL_CNTL3,
cntlbase + (unsigned long)(3 * 4));
writel(G12A_PCIE_PLL_CNTL4,
cntlbase + (unsigned long)(4 * 4));
writel(G12A_PCIE_PLL_CNTL5,
cntlbase + (unsigned long)(5 * 4));
writel(G12A_PCIE_PLL_CNTL5_,
cntlbase + (unsigned long)(5 * 4));
udelay(20);
writel(G12A_PCIE_PLL_CNTL4_,
cntlbase + (unsigned long)(4 * 4));
udelay(10);
/*set pcie_apll_afc_start bit*/
writel(G12A_PCIE_PLL_CNTL0_2,
cntlbase + (unsigned long)(0 * 4));
writel(G12A_PCIE_PLL_CNTL0_3,
cntlbase + (unsigned long)(0 * 4));
udelay(10);
writel(G12A_PCIE_PLL_CNTL2_,
cntlbase + (unsigned long)(2 * 4));
goto OUT;
} else if (!strcmp(clk_hw_get_name(hw), "sys_pll")) {
writel((readl(cntlbase) | MESON_PLL_RESET)
& (~MESON_PLL_ENABLE), cntlbase);
writel(G12A_SYS_PLL_CNTL1,
cntlbase + (unsigned long)(1 * 4));
writel(G12A_SYS_PLL_CNTL2,
cntlbase + (unsigned long)(2 * 4));
writel(G12A_SYS_PLL_CNTL3,
cntlbase + (unsigned long)(3 * 4));
writel(G12A_SYS_PLL_CNTL4,
cntlbase + (unsigned long)(4 * 4));
writel(G12A_SYS_PLL_CNTL5,
cntlbase + (unsigned long)(5 * 4));
writel(G12A_PLL_CNTL6,
cntlbase + (unsigned long)(6 * 4));
udelay(10);
} else if (!strcmp(clk_hw_get_name(hw), "sys1_pll")) {
writel((readl(cntlbase) | MESON_PLL_RESET)
& (~MESON_PLL_ENABLE), cntlbase);
writel(G12A_SYS1_PLL_CNTL1,
cntlbase + (unsigned long)(1 * 4));
writel(G12A_SYS1_PLL_CNTL2,
cntlbase + (unsigned long)(2 * 4));
writel(G12A_SYS1_PLL_CNTL3,
cntlbase + (unsigned long)(3 * 4));
writel(G12A_SYS1_PLL_CNTL4,
cntlbase + (unsigned long)(4 * 4));
writel(G12A_SYS1_PLL_CNTL5,
cntlbase + (unsigned long)(5 * 4));
writel(G12A_PLL_CNTL6,
cntlbase + (unsigned long)(6 * 4));
udelay(10);
} else if (!strcmp(clk_hw_get_name(hw), "gp0_pll") ||
!strcmp(clk_hw_get_name(hw), "gp1_pll")) {
writel((readl(cntlbase) | MESON_PLL_RESET)
& (~MESON_PLL_ENABLE), cntlbase);
writel(G12A_GP0_PLL_CNTL1,
cntlbase + (unsigned long)(1 * 4));
writel(G12A_GP0_PLL_CNTL2,
cntlbase + (unsigned long)(2 * 4));
writel(G12A_GP0_PLL_CNTL3,
cntlbase + (unsigned long)(3 * 4));
writel(G12A_GP0_PLL_CNTL4,
cntlbase + (unsigned long)(4 * 4));
writel(G12A_GP0_PLL_CNTL5,
cntlbase + (unsigned long)(5 * 4));
writel(G12A_PLL_CNTL6,
cntlbase + (unsigned long)(6 * 4));
udelay(10);
} else if (!strcmp(clk_hw_get_name(hw), "hifi_pll")) {
writel((readl(cntlbase) | MESON_PLL_RESET)
& (~MESON_PLL_ENABLE), cntlbase);
writel(G12A_HIFI_PLL_CNTL1,
cntlbase + (unsigned long)(1 * 4));
writel(G12A_HIFI_PLL_CNTL2,
cntlbase + (unsigned long)(2 * 4));
writel(G12A_HIFI_PLL_CNTL3,
cntlbase + (unsigned long)(3 * 4));
writel(G12A_HIFI_PLL_CNTL4,
cntlbase + (unsigned long)(4 * 4));
writel(G12A_HIFI_PLL_CNTL5,
cntlbase + (unsigned long)(5 * 4));
writel(G12A_PLL_CNTL6,
cntlbase + (unsigned long)(6 * 4));
udelay(10);
} else {
pr_err("%s: %s pll not found!!!\n",
__func__, clk_hw_get_name(hw));
return -EINVAL;
}
/* waiting for 50us to check is locked or not */
udelay(50);
/* lock bit is in the cntlbase */
if (readl(cntlbase + (unsigned long)(0 * 4))
& MESON_PLL_LOCK)
break;
j--;
} while (j);
reg = readl(pll->base + p->reg_off);