From a2b12fb2b691c8f28314ed66913daddecd009d2d Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Mon, 9 May 2022 20:05:18 +0800 Subject: [PATCH] video: rockchip: rga3: rga3 is compatible with RGA2's alpha_blend configuration 1. ABA -> ABB. 2. The output has an offset and is placed in win0 for processing. Signed-off-by: Yu Qiaowei Change-Id: Id501ad32fc887b6e88dfaec5cfdb1842169951bd --- .../video/rockchip/rga3/include/rga_common.h | 1 + drivers/video/rockchip/rga3/rga3_reg_info.c | 36 +++++++++++++++++-- drivers/video/rockchip/rga3/rga_common.c | 16 +++++++++ 3 files changed, 51 insertions(+), 2 deletions(-) diff --git a/drivers/video/rockchip/rga3/include/rga_common.h b/drivers/video/rockchip/rga3/include/rga_common.h index 3fa3e72c037f..12d15df390a2 100644 --- a/drivers/video/rockchip/rga3/include/rga_common.h +++ b/drivers/video/rockchip/rga3/include/rga_common.h @@ -33,6 +33,7 @@ const char *rga_get_blend_mode_str(uint16_t alpha_rop_flag, const char *rga_get_memory_type_str(uint8_t type); void rga_convert_addr(struct rga_img_info_t *img, bool before_vir_get_channel); +void rga_swap_pd_mode(struct rga_req *req_rga); int rga_image_size_cal(int w, int h, int format, int *yrgb_size, int *uv_size, int *v_size); diff --git a/drivers/video/rockchip/rga3/rga3_reg_info.c b/drivers/video/rockchip/rga3/rga3_reg_info.c index e3be5e525ac0..7666870e19b9 100644 --- a/drivers/video/rockchip/rga3/rga3_reg_info.c +++ b/drivers/video/rockchip/rga3/rga3_reg_info.c @@ -1278,6 +1278,7 @@ static void set_wr_info(struct rga_req *req_rga, struct rga3_req *req) void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req) { u16 alpha_mode_0, alpha_mode_1; + struct rga_img_info_t tmp; req->render_mode = BITBLT_MODE; @@ -1372,6 +1373,27 @@ void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req) req->win0.format = req_rga->src.format; req->wr.format = req_rga->dst.format; } else { + if (req_rga->pat.yrgb_addr != 0) { + if (req_rga->src.yrgb_addr == req_rga->dst.yrgb_addr) { + /* Convert ABC mode to ABB mode. */ + memcpy(&req_rga->src, &req_rga->pat, sizeof(req_rga->src)); + memset(&req_rga->pat, 0x0, sizeof(req_rga->pat)); + req_rga->bsfilter_flag = 0; + + rga_swap_pd_mode(req_rga); + } else if ((req_rga->dst.x_offset + req_rga->src.act_w > + req_rga->pat.act_w) || + (req_rga->dst.y_offset + req_rga->src.act_h > + req_rga->pat.act_h)) { + /* wr_offset + win1.act_size need > win0.act_size */ + memcpy(&tmp, &req_rga->src, sizeof(tmp)); + memcpy(&req_rga->src, &req_rga->pat, sizeof(req_rga->src)); + memcpy(&req_rga->pat, &tmp, sizeof(req_rga->pat)); + + rga_swap_pd_mode(req_rga); + } + } + set_win_info(&req->win1, &req_rga->src); /* enable win1 rotate */ @@ -1390,8 +1412,18 @@ void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req) req->win0.format = req_rga->pat.format; /* set win0 dst size */ - req->win0.dst_act_w = req_rga->pat.act_w; - req->win0.dst_act_h = req_rga->pat.act_h; + if (req->win0.x_offset || req->win0.y_offset) { + req->win0.src_act_w = req->win0.src_act_w + req->win0.x_offset; + req->win0.src_act_h = req->win0.src_act_h + req->win0.y_offset; + req->win0.dst_act_w = req_rga->pat.act_w + req->win0.x_offset; + req->win0.dst_act_h = req_rga->pat.act_h + req->win0.y_offset; + + req->win0.x_offset = 0; + req->win0.y_offset = 0; + } else { + req->win0.dst_act_w = req_rga->pat.act_w; + req->win0.dst_act_h = req_rga->pat.act_h; + } /* set win1 dst size */ req->win1.dst_act_w = req_rga->pat.act_w; req->win1.dst_act_h = req_rga->pat.act_h; diff --git a/drivers/video/rockchip/rga3/rga_common.c b/drivers/video/rockchip/rga3/rga_common.c index 73522b8ed735..60483aeb1a89 100644 --- a/drivers/video/rockchip/rga3/rga_common.c +++ b/drivers/video/rockchip/rga3/rga_common.c @@ -521,6 +521,22 @@ void rga_convert_addr(struct rga_img_info_t *img, bool before_vir_get_channel) } } +void rga_swap_pd_mode(struct rga_req *req_rga) +{ + if (((req_rga->alpha_rop_flag) & 1)) { + if ((req_rga->alpha_rop_flag >> 3) & 1) { + if (req_rga->PD_mode == 1) + req_rga->PD_mode = 2; + else if (req_rga->PD_mode == 2) + req_rga->PD_mode = 1; + else if (req_rga->PD_mode == 3) + req_rga->PD_mode = 4; + else if (req_rga->PD_mode == 4) + req_rga->PD_mode = 3; + } + } +} + int rga_image_size_cal(int w, int h, int format, int *yrgb_size, int *uv_size, int *v_size) {