From a3c954fda3e02ca759177564806274bb567adbda Mon Sep 17 00:00:00 2001
From: Algea Cao <algea.cao@rock-chips.com>
Date: Tue, 29 Mar 2022 09:41:53 +0800
Subject: [PATCH] phy: rockchip-samsung-hdptx-hdmi: Don't get rate when dclk
 enable

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I2aaf01140c681b07823a90ff046fa55621dce181
---
 drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c
index 875b1ead4d15..4e08968b1c44 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c
@@ -2076,7 +2076,6 @@ static int hdptx_phy_clk_enable(struct clk_hw *hw)
 		}
 	}
 
-	clk_get_rate(hdptx->dclk);
 	hdptx->count++;
 
 	return 0;