From a3da8a9f838277d5a8a14b93a817c1d56ed0799d Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Tue, 25 Mar 2025 09:38:30 +0800 Subject: [PATCH] video: rockchip: rga3: fix iommu pre-fetch threshold Signed-off-by: Yu Qiaowei Change-Id: Ic74f2d8136826484e019bb7fcbc31da0f9580e1e --- .../rockchip/rga3/include/rga2_reg_info.h | 10 ++++++++ drivers/video/rockchip/rga3/rga2_reg_info.c | 24 ++++++++++++++----- 2 files changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/video/rockchip/rga3/include/rga2_reg_info.h b/drivers/video/rockchip/rga3/include/rga2_reg_info.h index c39f53649e07..2aadfa65c9a6 100644 --- a/drivers/video/rockchip/rga3/include/rga2_reg_info.h +++ b/drivers/video/rockchip/rga3/include/rga2_reg_info.h @@ -242,6 +242,7 @@ #define m_RGA2_MODE_CTRL_SW_YIN_YOUT_EN (0x1<<10) #define m_RGA2_MODE_CTRL_SW_TILE4x4_IN_EN (0x1 << 12) #define m_RGA2_MODE_CTRL_SW_TILE4x4_OUT_EN (0x1 << 13) +#define m_RGA2_MODE_CTRL_SW_TABLE_PRE_FETCH_MODE (0x3 << 14) #define m_RGA2_MODE_CTRL_SW_FBC_IN_EN (0x1 << 16) #define m_RGA2_MODE_CTRL_SW_SRC_GAUSS_EN (0x1 << 17) #define m_RGA2_MODE_CTRL_SW_FBC_BSP_DIS (0x1 << 18) /* moved to RGA_BACKDOOR0 since RV1126B */ @@ -260,6 +261,7 @@ #define s_RGA2_MODE_CTRL_SW_YIN_YOUT_EN(x) ((x & 0x1) << 10) #define s_RGA2_MODE_CTRL_SW_TILE4x4_IN_EN(x) ((x & 0x1) << 12) #define s_RGA2_MODE_CTRL_SW_TILE4x4_OUT_EN(x) ((x & 0x1) << 13) +#define s_RGA2_MODE_CTRL_SW_TABLE_PRE_FETCH_MODE(x) ((x & 0x3) << 14) #define s_RGA2_MODE_CTRL_SW_FBC_IN_EN(x) ((x & 0x1) << 16) #define s_RGA2_MODE_CTRL_SW_SRC_GAUSS_EN(x) ((x & 0x1) << 17) #define s_RGA2_MODE_CTRL_SW_FBC_BSP_DIS(x) ((x & 0x1) << 18) @@ -519,6 +521,14 @@ #define RGA2_VSP_BICUBIC_LIMIT 1996 #define RGA2_BILINEAR_PREC 12 +#define RGA2_IOMMU_PREFETCH_SHIFT 16 +#define RGA2_IOMMU_PREFETCH_MASK 0xffff +#define RGA2_IOMMU_PREFETCH_ALIGN(x) \ + (((x) + RGA2_IOMMU_PREFETCH_MASK) & ~RGA2_IOMMU_PREFETCH_MASK) +#define RGA2_IOMMU_PREFETCH_ALIGN_DOWN(x) ((x) & ~RGA2_IOMMU_PREFETCH_MASK) +#define RGA2_IOMMU_PREFETCH_THRESHOLD_MIN (0x1U << RGA2_IOMMU_PREFETCH_SHIFT) +#define RGA2_IOMMU_PREFETCH_THRESHOLD_MAX (0xffffU << RGA2_IOMMU_PREFETCH_SHIFT) + union rga2_color_ctrl { uint32_t value; struct { diff --git a/drivers/video/rockchip/rga3/rga2_reg_info.c b/drivers/video/rockchip/rga3/rga2_reg_info.c index 49d333acf3eb..09c4acd31dfe 100644 --- a/drivers/video/rockchip/rga3/rga2_reg_info.c +++ b/drivers/video/rockchip/rga3/rga2_reg_info.c @@ -297,6 +297,9 @@ static void RGA2_set_mode_ctrl(u8 *base, struct rga2_req *msg) reg = ((reg & (~m_RGA2_MODE_CTRL_SW_TILE4x4_OUT_EN)) | (s_RGA2_MODE_CTRL_SW_TILE4x4_OUT_EN(1))); + reg = ((reg & (~m_RGA2_MODE_CTRL_SW_TABLE_PRE_FETCH_MODE)) | + (s_RGA2_MODE_CTRL_SW_TABLE_PRE_FETCH_MODE(0))); /* 128k */ + if (msg->src.rd_mode == RGA_RKFBC_MODE || msg->src.rd_mode == RGA_AFBC32x8_MODE) reg = ((reg & (~m_RGA2_MODE_CTRL_SW_FBC_IN_EN)) | (s_RGA2_MODE_CTRL_SW_FBC_IN_EN(1))); @@ -1668,11 +1671,19 @@ static void RGA2_set_reg_dst_info(u8 *base, struct rga2_req *msg) if (rot_90_flag == 1) { if (y_mirr == 1) { - msg->iommu_prefetch.y_threshold = y_lt_addr; - msg->iommu_prefetch.uv_threshold = u_lt_addr; + msg->iommu_prefetch.y_threshold = y_lt_addr >> 16 ? + RGA2_IOMMU_PREFETCH_ALIGN_DOWN(y_lt_addr) : + RGA2_IOMMU_PREFETCH_THRESHOLD_MIN; + msg->iommu_prefetch.uv_threshold = u_lt_addr >> 16 ? + RGA2_IOMMU_PREFETCH_ALIGN_DOWN(u_lt_addr) : + RGA2_IOMMU_PREFETCH_THRESHOLD_MIN; } else { - msg->iommu_prefetch.y_threshold = y_rd_addr; - msg->iommu_prefetch.uv_threshold = u_rd_addr; + msg->iommu_prefetch.y_threshold = (y_rd_addr >> 16) == 0xffff ? + RGA2_IOMMU_PREFETCH_THRESHOLD_MAX : + RGA2_IOMMU_PREFETCH_ALIGN(y_rd_addr); + msg->iommu_prefetch.uv_threshold = (u_rd_addr >> 16) == 0xffff ? + RGA2_IOMMU_PREFETCH_THRESHOLD_MAX : + RGA2_IOMMU_PREFETCH_ALIGN(u_rd_addr); } } } @@ -2326,8 +2337,9 @@ static void RGA2_set_mmu_reg_info(struct rga_scheduler_t *scheduler, u8 *base, s case RGA_IOMMU: RGA_PREFETCH_ADDR_TH = (u32 *)(base + RGA2_PREFETCH_ADDR_TH_OFFSET); - *RGA_PREFETCH_ADDR_TH = (msg->iommu_prefetch.y_threshold >> 16) | - ((msg->iommu_prefetch.uv_threshold >> 16) << 16); + *RGA_PREFETCH_ADDR_TH = + (msg->iommu_prefetch.y_threshold >> RGA2_IOMMU_PREFETCH_SHIFT) | + ((msg->iommu_prefetch.uv_threshold >> RGA2_IOMMU_PREFETCH_SHIFT) << 16); break; default: break;