diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi
index b521d10bb621..b79a8d5e9824 100644
--- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi
@@ -1021,6 +1021,40 @@
 		status = "disabled";
 	};
 
+	cif: cif@ffae0000 {
+		compatible = "rockchip,rk1808-cif";
+		reg = <0x0 0xffae0000 0x0 0x200>, <0x0 0xffb10000 0x0 0x100>;
+		reg-names = "cif_regs", "csihost_regs";
+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_CIF>, <&cru DCLK_CIF>,
+			 <&cru HCLK_CIF>, <&cru SCLK_CIF_OUT>,
+			 <&cru PCLK_CSI2HOST>;
+		clock-names = "aclk_cif", "dclk_cif",
+			"hclk_cif", "sclk_cif_out",
+			"pclk_csi2host";
+		resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>,
+			 <&cru SRST_CIF_I>, <&cru SRST_CIF_D>,
+			 <&cru SRST_CIF_PCLKIN>;
+		reset-names = "rst_cif_a", "rst_cif_h",
+			"rst_cif_i", "rst_cif_d",
+			"rst_cif_pclkin";
+		power-domains = <&power RK1808_PD_VIO>;
+		iommus = <&cif_mmu>;
+		status = "disabled";
+	};
+
+	cif_mmu: iommu@ffae0800 {
+		compatible = "rockchip,iommu";
+		reg = <0x0 0xffae0800 0x0 0x100>;
+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "cif_mmu";
+		clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>;
+		clock-names = "aclk", "hclk";
+		power-domains = <&power RK1808_PD_VIO>;
+		#iommu-cells = <0>;
+		status = "disabled";
+	};
+
 	vop_lite: vop@ffb00000 {
 		compatible = "rockchip,rk1808-vop-lit";
 		reg = <0x0 0xffb00000 0x0 0x200>;