From ab970f79e38409fc164f2f40cfcb64a067ad4518 Mon Sep 17 00:00:00 2001 From: Binyuan Lan Date: Sun, 15 Sep 2024 17:36:22 +0800 Subject: [PATCH 1/4] ASoC: rk817: Resolve POP noise when starting recording during playback During the playback, if PLL_PW_DOWN and PLL_PW_UP is performed, a POP sound is generated. When the sample rate does not change, do not restart the pll. Change-Id: I83de976e6e2752a85c57fbc4d4eb6bd5f1b21fbf Signed-off-by: Binyuan Lan --- sound/soc/codecs/rk817_codec.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/sound/soc/codecs/rk817_codec.c b/sound/soc/codecs/rk817_codec.c index 2b53c637dc8e..a60960a2c91c 100644 --- a/sound/soc/codecs/rk817_codec.c +++ b/sound/soc/codecs/rk817_codec.c @@ -542,6 +542,7 @@ static int rk817_codec_power_up(struct snd_soc_component *component, int type) static int rk817_codec_power_down(struct snd_soc_component *component, int type) { + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); int i; DBG("%s : power down %s %s %s\n", __func__, @@ -592,6 +593,7 @@ static int rk817_codec_power_down(struct snd_soc_component *component, int type) snd_soc_component_write(component, RK817_CODEC_DTOP_DIGEN_CLKE, 0x00); snd_soc_component_write(component, RK817_CODEC_APLL_CFG5, 0x01); snd_soc_component_write(component, RK817_CODEC_AREF_RTCFG1, 0x06); + rk817->rate = 0; } return 0; @@ -1041,19 +1043,12 @@ static int rk817_set_dai_sysclk(struct snd_soc_dai *codec_dai, { struct snd_soc_component *component = codec_dai->component; struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); - unsigned int ret = 0; - ret = clk_set_rate(rk817->mclk, freq); - if (ret) { - dev_warn(component->dev, "%s %d clk_set_rate %d failed\n", - __func__, __LINE__, freq); - return ret; - } rk817->stereo_sysclk = freq; DBG("%s : MCLK = %dHz\n", __func__, rk817->stereo_sysclk); - return ret; + return 0; } static int rk817_set_dai_fmt(struct snd_soc_dai *codec_dai, @@ -1090,8 +1085,9 @@ static int rk817_hw_params(struct snd_pcm_substream *substream, unsigned int rate = params_rate(params); unsigned char apll_cfg3_val; unsigned char dtop_digen_sr_lmt0; + unsigned int ret = 0; - DBG("%s : sample rate = %dHz\n", __func__, rate); + DBG("%s : pre sample rate = %d, cur sample rate = %dHz\n", __func__, rk817->rate, rate); if (rk817->chip_ver <= 0x4) { DBG("%s: 0x4 and previous versions\n", __func__); @@ -1132,7 +1128,12 @@ static int rk817_hw_params(struct snd_pcm_substream *substream, * is before playback/capture_path_put, therefore, we need to configure * APLL_CFG3/DTOP_DIGEN_CLKE/DDAC_SR_LMT0 for different sample rates. */ - if (!((substream->stream == SNDRV_PCM_STREAM_CAPTURE) && rk817->pdmdata_out_enable)) { + if ((rk817->rate != rate) && + !((substream->stream == SNDRV_PCM_STREAM_CAPTURE) && rk817->pdmdata_out_enable)) { + ret = clk_set_rate(rk817->mclk, rk817->stereo_sysclk); + if (ret) + dev_warn(component->dev, "%s %d clk_set_rate %d failed\n", + __func__, __LINE__, rk817->stereo_sysclk); snd_soc_component_write(component, RK817_CODEC_APLL_CFG3, apll_cfg3_val); snd_soc_component_update_bits(component, RK817_CODEC_DDAC_SR_LMT0, DACSRT_MASK, dtop_digen_sr_lmt0); @@ -1142,6 +1143,8 @@ static int rk817_hw_params(struct snd_pcm_substream *substream, rk817_restart_adc_digital_clk_and_apll(component); } + rk817->rate = rate; + switch (params_format(params)) { case SNDRV_PCM_FORMAT_S16_LE: snd_soc_component_write(component, RK817_CODEC_DI2S_RXCR2, @@ -1378,6 +1381,7 @@ static int rk817_probe(struct snd_soc_component *component) rk817->component = component; rk817->playback_path = OFF; rk817->capture_path = MIC_OFF; + rk817->rate = 0; chip_name = snd_soc_component_read(component, RK817_PMIC_CHIP_NAME); chip_ver = snd_soc_component_read(component, RK817_PMIC_CHIP_VER); From 35551a65407947073d205f7c1e1e1db772328a5b Mon Sep 17 00:00:00 2001 From: Ye Zhang Date: Sun, 29 Sep 2024 20:10:51 +0800 Subject: [PATCH 2/4] gpio: rockchip: don't use debounce config function Since Rockchip's GPIO hardware debounce function does not support configuring individual pins, it will not be used. Partially revert commit 2af76b32134d ("gpio: rockchip: Update debounce config function"). Signed-off-by: Ye Zhang Change-Id: I3c9fd877643aaac3816181a61052d395c95c6593 --- drivers/gpio/gpio-rockchip.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c index 4672c491b530..4a0c12a2808d 100644 --- a/drivers/gpio/gpio-rockchip.c +++ b/drivers/gpio/gpio-rockchip.c @@ -292,11 +292,15 @@ static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, unsigned long config) { enum pin_config_param param = pinconf_to_config_param(config); - unsigned int debounce = pinconf_to_config_argument(config); switch (param) { case PIN_CONFIG_INPUT_DEBOUNCE: - return rockchip_gpio_set_debounce(gc, offset, debounce); + rockchip_gpio_set_debounce(gc, offset, 0); + /* + * Since Rockchip's GPIO hardware debounce function does not + * support configuring individual pins, it will not be used. + */ + return -ENOTSUPP; default: return -ENOTSUPP; } From 4aa5b7a0fa4c5b2ab10a104cc72c85f81d3a94f2 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Mon, 30 Sep 2024 14:38:14 +0800 Subject: [PATCH 3/4] drm/bridge: synopsys: dw-hdmi-qp: Don't read scdc regs with hdmi1.4 sink Only hdmi2.0 and later versions support scdc. Change-Id: Ice2079afe38e624ef7a0dbb2a67f6c8c5d5ba58d Signed-off-by: Algea Cao --- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c index 8e9208095563..1e952e1bbbe8 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -3179,7 +3179,9 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true); } - drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &val); + val = 0; + if (dw_hdmi_support_scdc(hdmi, &connector->display_info)) + drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &val); /* if plug out before hdmi bind, reset hdmi */ if (vmode->mtmdsclock >= 340000000 && vmode->mpixelclock <= 600000000 && !(val & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) && !hdmi->force_kernel_output) From f131a6b432efe9c3fdc78370e569af4e3eb4cf64 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Sun, 29 Sep 2024 15:35:22 +0800 Subject: [PATCH 4/4] drm/rockchip: vop2: move frc v2 dither config to crtc aotmic enable Signed-off-by: Sandy Huang Change-Id: I29e876ca7328909066f16827270d9427ceae7862 --- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 3 +++ drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 14 +++----------- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 6 ++++++ drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 3 +++ 4 files changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 8d5729c8b943..690d882689ee 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -898,6 +898,9 @@ struct vop2_video_port_regs { struct vop_reg dither_down_mode; struct vop_reg dither_down_en; struct vop_reg pre_dither_down_en; + struct vop_reg dither_frc_0; + struct vop_reg dither_frc_1; + struct vop_reg dither_frc_2; struct vop_reg dither_up_en; struct vop_reg bg_dly; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 545f75e638d8..147a7f44feb3 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -4383,14 +4383,6 @@ static void vop2_initial(struct drm_crtc *crtc) /* Default use rkiommu 1.0 for axi0 */ VOP_CTRL_SET(vop2, rkmmu_v2_en, 0); - /* Init frc2.0 config */ - vop2_writel(vop2, 0xca0, 0xc8); - vop2_writel(vop2, 0xca4, 0x01000100); - vop2_writel(vop2, 0xca8, 0x03ff0100); - vop2_writel(vop2, 0xda0, 0xc8); - vop2_writel(vop2, 0xda4, 0x01000100); - vop2_writel(vop2, 0xda8, 0x03ff0100); - if (vop2->merge_irq == true) VOP_CTRL_SET(vop2, vp_intr_merge_en, 1); VOP_CTRL_SET(vop2, lut_use_axi1, 0); @@ -8103,9 +8095,9 @@ static void vop2_dither_setup(struct rockchip_crtc_state *vcstate, struct drm_cr pre_dither_down_en = false; if (vp_data->feature & VOP_FEATURE_POST_FRC_V2 && pre_dither_down_en) { - vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_0, 0x00000000); - vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_1, 0x01000100); - vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_2, 0x04030100); + VOP_MODULE_SET(vop2, vp, dither_frc_0, 0x00000000); + VOP_MODULE_SET(vop2, vp, dither_frc_1, 0x01000100); + VOP_MODULE_SET(vop2, vp, dither_frc_2, 0x04030100); VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 0); VOP_MODULE_SET(vop2, vp, dither_down_en, 1);/* enable frc2.0 do 10->8 */ diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index 9577d9930db8..c82ae2c5bfe9 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -1487,6 +1487,9 @@ static const struct vop2_video_port_regs rk3576_vop_vp0_regs = { .post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15), .pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16), .dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17), + .dither_frc_0 = VOP_REG(RK3576_VP0_POST_DITHER_FRC_0, 0xffffffff, 0), + .dither_frc_1 = VOP_REG(RK3576_VP0_POST_DITHER_FRC_1, 0xffffffff, 0), + .dither_frc_2 = VOP_REG(RK3576_VP0_POST_DITHER_FRC_2, 0xffffffff, 0), .dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18), .dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20), .gamma_update_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 22), @@ -1600,6 +1603,9 @@ static const struct vop2_video_port_regs rk3576_vop_vp1_regs = { .post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15), .pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16), .dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17), + .dither_frc_0 = VOP_REG(RK3576_VP1_POST_DITHER_FRC_0, 0xffffffff, 0), + .dither_frc_1 = VOP_REG(RK3576_VP1_POST_DITHER_FRC_1, 0xffffffff, 0), + .dither_frc_2 = VOP_REG(RK3576_VP1_POST_DITHER_FRC_2, 0xffffffff, 0), .dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18), .dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20), .gamma_update_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 22), diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index 94b9f3a28a80..458185b38bb0 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -1201,6 +1201,9 @@ #define RK3568_VP1_BCSH_BCS 0xD64 #define RK3568_VP1_BCSH_H 0xD68 #define RK3568_VP1_BCSH_COLOR_BAR 0xD6C +#define RK3576_VP1_POST_DITHER_FRC_0 0xDA0 +#define RK3576_VP1_POST_DITHER_FRC_1 0xDA4 +#define RK3576_VP1_POST_DITHER_FRC_2 0xDA8 #define RK3562_VP1_MCU_CTRL 0xDF8 #define RK3562_VP1_MCU_RW_BYPASS_PORT 0xDFC