From a44f986d11c132caee6e380c22f8cff5058ce615 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Sun, 14 Nov 2021 21:29:43 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588: Add pcie1ln setting for comboPHY The controller must route to the comboPHY when it works. pcie1l0_sel Select the signal form PHY to PCIe1l0 1'b0: Select comb PHY 1'b1: Select PCIE3 PHY Signed-off-by: Kever Yang Change-Id: I5e7faf71fdd22958c757f884f75ec9a00aeb2fb9 --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 1de0e7fa7dc2..0d4f7c4a3aee 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -687,6 +687,7 @@ reset-names = "combphy-apb", "combphy"; rockchip,pipe-grf = <&php_grf>; rockchip,pipe-phy-grf = <&pipe_phy1_grf>; + rockchip,pcie1ln-sel-bits = <0x100 1 1 0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index ed7854fc9e10..f340050a81a3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -3846,6 +3846,7 @@ reset-names = "combphy-apb", "combphy"; rockchip,pipe-grf = <&php_grf>; rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + rockchip,pcie1ln-sel-bits = <0x100 0 0 0>; status = "disabled"; };