From a56129cb0cc9556653dae72872f9deaf7aa8a399 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 20 Jan 2025 17:21:58 +0800 Subject: [PATCH] Revert "clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228" This reverts commit a3f77b5d16e3e8e6ce198e4840bd1938e82491e8. RK3228 Only GPLL and CPLL, GPLL is a common clock, does not allow dclk_vop to change its frequency, CPLL is used by GMAC, if dclk_vop use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags will affect the GMAC function. Change-Id: I2c959a19f115b34720364586c374fc6e01fc8eb4 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3228.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c index 4a07f99dbd48..04e75861eb18 100644 --- a/drivers/clk/rockchip/clk-rk3228.c +++ b/drivers/clk/rockchip/clk-rk3228.c @@ -410,7 +410,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), - MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0, RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), FACTOR(0, "xin12m", "xin24m", 0, 1, 2),