From a561d683acecd8053f59b7c7ea8ea4adbf313128 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Mon, 5 Feb 2018 15:38:17 +0800 Subject: [PATCH] clk: rockchip: rk3228: add clk_ddrc for devfreq of ddr Change-Id: I3771e2ef68ab3fa8ad1b7d61a84c7181c693c60f Signed-off-by: Liang Chen Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3228.c | 13 +++++-------- include/dt-bindings/clock/rk3228-cru.h | 1 + 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c index 376457a129ba..e0d9bcff4572 100644 --- a/drivers/clk/rockchip/clk-rk3228.c +++ b/drivers/clk/rockchip/clk-rk3228.c @@ -226,15 +226,12 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { RK2928_CLKSEL_CON(4), 8, 5, DFLAGS), /* PD_DDR */ - COMPOSITE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED, - RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, - RK2928_CLKGATE_CON(0), 2, GFLAGS), - GATE(0, "ddrphy4x", "clk_ddrphy_src", CLK_IGNORE_UNUSED, + COMPOSITE_DDRCLK(SCLK_DDRC, "clk_ddrc", mux_ddrphy_p, 0, + RK2928_CLKSEL_CON(26), 8, 2, 0, 2, + ROCKCHIP_DDRCLK_SIP_V2), + FACTOR(0, "clk_ddrphy", "clk_ddrc", 0, 1, 4), + GATE(0, "ddrphy4x", "clk_ddrc", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 1, GFLAGS), - FACTOR_GATE(0, "ddrc", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4, - RK2928_CLKGATE_CON(8), 5, GFLAGS), - FACTOR_GATE(0, "ddrphy", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4, - RK2928_CLKGATE_CON(7), 0, GFLAGS), /* PD_CORE */ GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index 9b2aaa3110cc..2f22a7b1538d 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -73,6 +73,7 @@ #define SCLK_WIFI 141 #define SCLK_OTGPHY0 142 #define SCLK_OTGPHY1 143 +#define SCLK_DDRC 144 /* dclk gates */ #define DCLK_VOP 190