From a5e8ecade214b0c524e21b6bce4e078ca9d6fdb0 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Tue, 30 Mar 2021 16:11:35 +0100 Subject: [PATCH] UPSTREAM: PCI: xilinx: Don't allocate extra memory for the MSI capture address A long cargo-culted behaviour of PCI drivers is to allocate memory to obtain an address that is fed to the controller as the MSI capture address (i.e. the MSI doorbell). But there is no actual requirement for this address to be RAM. All it needs to be is a suitable aligned address that will *not* be DMA'd to. Use the physical address of the 'port' data structure as the MSI capture address, aligned on a 4K boundary. Link: https://lore.kernel.org/r/20210330151145.997953-5-maz@kernel.org Tested-by: Bharat Kumar Gogada Signed-off-by: Marc Zyngier Signed-off-by: Lorenzo Pieralisi (cherry picked from commit 161260e7f7bc58d6a0972eb41a6072e82d0b58a5) Signed-off-by: Marc Zyngier Change-Id: I2b3573098b416f3ec5bc2438dc13e4af46b8b0a4 Bug: 187801341 --- drivers/pci/controller/pcie-xilinx.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx.c b/drivers/pci/controller/pcie-xilinx.c index 8523be61bba5..938cff1bb42f 100644 --- a/drivers/pci/controller/pcie-xilinx.c +++ b/drivers/pci/controller/pcie-xilinx.c @@ -97,7 +97,6 @@ * struct xilinx_pcie_port - PCIe port information * @reg_base: IO Mapped Register Base * @irq: Interrupt number - * @msi_pages: MSI pages * @dev: Device pointer * @msi_domain: MSI IRQ domain pointer * @leg_domain: Legacy IRQ domain pointer @@ -106,7 +105,6 @@ struct xilinx_pcie_port { void __iomem *reg_base; u32 irq; - unsigned long msi_pages; struct device *dev; struct irq_domain *msi_domain; struct irq_domain *leg_domain; @@ -281,10 +279,10 @@ static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip, irq_set_msi_desc(irq, desc); - msg_addr = virt_to_phys((void *)port->msi_pages); + msg_addr = ALIGN_DOWN(virt_to_phys(port), SZ_4K); - msg.address_hi = 0; - msg.address_lo = msg_addr; + msg.address_hi = upper_32_bits(msg_addr); + msg.address_lo = lower_32_bits(msg_addr); msg.data = irq; pci_write_msi_msg(irq, &msg); @@ -337,13 +335,9 @@ static int xilinx_pcie_enable_msi(struct xilinx_pcie_port *port) { phys_addr_t msg_addr; - port->msi_pages = __get_free_pages(GFP_KERNEL, 0); - if (!port->msi_pages) - return -ENOMEM; - - msg_addr = virt_to_phys((void *)port->msi_pages); - pcie_write(port, 0x0, XILINX_PCIE_REG_MSIBASE1); - pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2); + msg_addr = ALIGN_DOWN(virt_to_phys(port), SZ_4K); + pcie_write(port, upper_32_bits(msg_addr), XILINX_PCIE_REG_MSIBASE1); + pcie_write(port, lower_32_bits(msg_addr), XILINX_PCIE_REG_MSIBASE2); return 0; }