From a601d1332ef5a6ed355daf25d15f8bcbc144e1ff Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Tue, 30 Jan 2024 10:38:55 +0800 Subject: [PATCH] drm/rockchip: analogix_dp: add mem_clk_auto_gating config Reg mem_clk_auto_gating can help to gate the clock for accessing HDCP memory automatically. Change-Id: I04188d59e4273cfb61551cd01ca53f336d2bf1aa Signed-off-by: Damon Ding --- drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index 6cb7cc03e551..d6ddbc8e4b1c 100644 --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c @@ -54,6 +54,7 @@ struct rockchip_grf_reg_field { * @spdif_sel: grf register field of spdif_sel * @i2s_sel: grf register field of i2s_sel * @edp_mode: grf register field of edp_mode + * @mem_clk_auto_gating: grf register field of mem_clk_auto_gating * @chip_type: specific chip type * @ssc: check if SSC is supported by source * @audio: check if audio is supported by source @@ -64,6 +65,7 @@ struct rockchip_dp_chip_data { const struct rockchip_grf_reg_field spdif_sel; const struct rockchip_grf_reg_field i2s_sel; const struct rockchip_grf_reg_field edp_mode; + const struct rockchip_grf_reg_field mem_clk_auto_gating; u32 chip_type; bool ssc; bool audio; @@ -392,6 +394,10 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder, if (old_crtc_state && old_crtc_state->self_refresh_active) return; + ret = rockchip_grf_field_write(dp->grf, &dp->data->mem_clk_auto_gating, 1); + if (ret != 0) + DRM_DEV_ERROR(dp->dev, "Could not write to GRF reg mem_clk_auto_gating: %d\n", ret); + ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder); if (ret < 0) return; @@ -400,7 +406,7 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder, ret = rockchip_grf_field_write(dp->grf, &dp->data->lcdc_sel, ret); if (ret != 0) - DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret); + DRM_DEV_ERROR(dp->dev, "Could not write to GRF reg lcdc_sel: %d\n", ret); } static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder, @@ -826,6 +832,7 @@ static const struct rockchip_dp_chip_data rk3576_edp[] = { .chip_type = RK3588_EDP, .spdif_sel = GRF_REG_FIELD(0x0000, 5, 5), .i2s_sel = GRF_REG_FIELD(0x0000, 4, 4), + .mem_clk_auto_gating = GRF_REG_FIELD(0x0020, 1, 1), .ssc = true, .audio = true, .split_mode = true,