From a616fed5f873b4b2d142ff3b14dbef95ddfd8d6f Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Tue, 9 Jul 2019 09:13:34 +0800 Subject: [PATCH] Revert "drm/rockchip/dsi: enable the grf clk before writing grf registers" This reverts commit 5bc07b1569022b403be2f92777430345dbbe39e4. Change-Id: Ifb9363ab30c139f41e2ee69fba97c9ec5bfcca1b Signed-off-by: Wyon Bi --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 26 +------------------------- 1 file changed, 1 insertion(+), 25 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 662b6cb5d3f0..4b2c3e3036e8 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -252,7 +252,6 @@ #define THS_ZERO_PROGRAM_EN BIT(6) #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) -#define DW_MIPI_NEEDS_GRF_CLK BIT(1) enum { BANDGAP_97_07, @@ -295,7 +294,6 @@ struct dw_mipi_dsi { struct regmap *grf_regmap; void __iomem *base; - struct clk *grf_clk; struct clk *pllref_clk; struct clk *pclk; struct clk *phy_cfg_clk; @@ -990,17 +988,6 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) dw_mipi_dsi_dphy_interface_config(dsi); dw_mipi_dsi_clear_err(dsi); - /* - * For the RK3399, the clk of grf must be enabled before writing grf - * register. And for RK3288 or other soc, this grf_clk must be NULL, - * the clk_prepare_enable return true directly. - */ - ret = clk_prepare_enable(dsi->grf_clk); - if (ret) { - DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); - return; - } - if (pdata->grf_dsi0_mode_reg) regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg, pdata->grf_dsi0_mode); @@ -1026,8 +1013,6 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) DRM_DEV_DEBUG(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG"); dsi->dpms_mode = DRM_MODE_DPMS_ON; - - clk_disable_unprepare(dsi->grf_clk); } static int @@ -1160,7 +1145,7 @@ static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = { .grf_switch_reg = RK3399_GRF_SOC_CON20, .grf_dsi0_mode = RK3399_GRF_DSI_MODE, .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22, - .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, + .flags = DW_MIPI_NEEDS_PHY_CFG_CLK, .max_data_lanes = 4, }; @@ -1261,15 +1246,6 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, } } - if (pdata->flags & DW_MIPI_NEEDS_GRF_CLK) { - dsi->grf_clk = devm_clk_get(dev, "grf"); - if (IS_ERR(dsi->grf_clk)) { - ret = PTR_ERR(dsi->grf_clk); - DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret); - return ret; - } - } - ret = clk_prepare_enable(dsi->pllref_clk); if (ret) { DRM_DEV_ERROR(dev, "Failed to enable pllref_clk\n");