From a648efab5ea2866d34843093083998bf1469db76 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Wed, 7 Sep 2022 11:26:51 +0800 Subject: [PATCH] phy: rockchip-naneng-combo: Add ssc support for pcie Best parameter: 24M T0_1 650mV. Should co-work with change like below: &combphy0_ps { + rockchip,enable-ssc; + assigned-clock-rates = <24000000>; status = "okay"; }; Signed-off-by: Kever Yang Change-Id: I863b8d1758431c0037332e7da1b2c64cd7113573 --- .../rockchip/phy-rockchip-naneng-combphy.c | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 6f7aa8ebc292..f32b831b941b 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -664,6 +664,12 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) switch (priv->mode) { case PHY_TYPE_PCIE: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x7c); + param_write(priv->phy_grf, &cfg->con0_for_pcie, true); param_write(priv->phy_grf, &cfg->con1_for_pcie, true); param_write(priv->phy_grf, &cfg->con2_for_pcie, true); @@ -841,6 +847,26 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) } } + if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) { + val = readl(priv->mmio + (0x7 << 2)); + val |= BIT(4); + writel(val, priv->mmio + (0x7 << 2)); + + if (priv->mode == PHY_TYPE_PCIE && rate == 24000000) { + /* Xin24M T0_1 650mV */ + writel(0x00, priv->mmio + (0x10 << 2)); + writel(0x32, priv->mmio + (0x11 << 2)); + writel(0x00, priv->mmio + (0x1b << 2)); + writel(0x90, priv->mmio + (0x0a << 2)); + writel(0x02, priv->mmio + (0x0b << 2)); + writel(0x08, priv->mmio + (0x0c << 2)); + writel(0x57, priv->mmio + (0x0d << 2)); + writel(0x40, priv->mmio + (0x0e << 2)); + writel(0x5f, priv->mmio + (0x0f << 2)); + writel(0x10, priv->mmio + (0x20 << 2)); + } + } + return 0; }