From a662526fcbe1281b7dcdb74c136feb87eab99646 Mon Sep 17 00:00:00 2001
From: Sandy Huang <hjc@rock-chips.com>
Date: Thu, 26 Oct 2023 10:20:19 +0800
Subject: [PATCH] drm/fourcc: add and update rockchip modifier format define

1. update rockchip tiled modifier format define;
2. add rockchip rfbc modifier format define, rfbc is rockchip framebuffer
compression format, it's will supported by rockchip video decoder, RGA and VOP
modules, and the superblocks size is 64x4.

Fixes: f727d3ad8e73 ("drm/fourcc: Add definitions for Rockchip vendor and VPU tiled format")
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ice06eda4819254ba670a7231836cabe46bc38137
---
 include/uapi/drm/drm_fourcc.h | 33 +++++++++++++++++++++++++++++++--
 1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index bedc59d650ae..604e47013087 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -1059,14 +1059,43 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
  */
 #define AMLOGIC_FBC_OPTION_MEM_SAVING		(1ULL << 0)
 
+/*
+ * Rockchip modifier format
+ * tiled modifier format, block size: 8x8,4x4_m0 and 4x4_m1,
+ * rfbc modifier format, block size: 64x4
+ *
+ * bit[55,52] for Rockchip drm modifier type
+ */
+#define DRM_FORMAT_MOD_ROCKCHIP_TYPE_SHIFT	52
+#define DRM_FORMAT_MOD_ROCKCHIP_TYPE_MASK	0xf
+#define DRM_FORMAT_MOD_ROCKCHIP_TYPE_TILED	0x0
+#define DRM_FORMAT_MOD_ROCKCHIP_TYPE_RFBC	0x1
+
+/* bit[3,0] for Rockchip drm modifier block size */
 #define ROCKCHIP_TILED_BLOCK_SIZE_MASK		0xf
 #define ROCKCHIP_TILED_BLOCK_SIZE_8x8		(1ULL)
 #define ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0	(2ULL)
 #define ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE1	(3ULL)
 
-#define DRM_FORMAT_MOD_ROCKCHIP_TILED(_mode) fourcc_mod_code(ROCKCHIP, _mode)
+#define ROCKCHIP_RFBC_BLOCK_SIZE_64x4		(1ULL)
 
-#define IS_ROCKCHIP_TILED_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_ROCKCHIP)
+#define DRM_FORMAT_MOD_ROCKCHIP_CODE(__type, __val) \
+	fourcc_mod_code(ROCKCHIP, ((__u64)(__type) << DRM_FORMAT_MOD_ROCKCHIP_TYPE_SHIFT) | \
+			((__val) & 0x000fffffffffffffULL))
+
+/* Rockchip tiled modifier format */
+#define DRM_FORMAT_MOD_ROCKCHIP_TILED(mode) \
+	DRM_FORMAT_MOD_ROCKCHIP_CODE(DRM_FORMAT_MOD_ROCKCHIP_TYPE_TILED, mode)
+#define IS_ROCKCHIP_TILED_MOD(val) \
+	(((val) >> 56) == DRM_FORMAT_MOD_VENDOR_ROCKCHIP && \
+	 ((val >> DRM_FORMAT_MOD_ROCKCHIP_TYPE_SHIFT) & DRM_FORMAT_MOD_ROCKCHIP_TYPE_MASK) == DRM_FORMAT_MOD_ROCKCHIP_TYPE_TILED)
+
+/* Rockchip rfbc modifier format */
+#define DRM_FORMAT_MOD_ROCKCHIP_RFBC(mode) \
+	DRM_FORMAT_MOD_ROCKCHIP_CODE(DRM_FORMAT_MOD_ROCKCHIP_TYPE_RFBC, mode)
+#define IS_ROCKCHIP_RFBC_MOD(val) \
+	(((val) >> 56) == DRM_FORMAT_MOD_VENDOR_ROCKCHIP && \
+	 ((val >> DRM_FORMAT_MOD_ROCKCHIP_TYPE_SHIFT) & DRM_FORMAT_MOD_ROCKCHIP_TYPE_MASK) == DRM_FORMAT_MOD_ROCKCHIP_TYPE_RFBC)
 
 #if defined(__cplusplus)
 }