From a66d9bdbbe8d8589db8e666b6fdf8dfe5f5e70bd Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 5 Jun 2024 14:51:46 +0800 Subject: [PATCH] clk: rockchip: rk3576: export pclk_hdptx_apb For edp and hdmi phy low power mode. Signed-off-by: Elaine Zhang Change-Id: I288be0ffbf50a7ed78614d4813c5d4f8508d7405 --- drivers/clk/rockchip/clk-rk3576.c | 2 ++ include/dt-bindings/clock/rockchip,rk3576-cru.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3576.c b/drivers/clk/rockchip/clk-rk3576.c index abbbab4df754..cfc52555ce8f 100644 --- a/drivers/clk/rockchip/clk-rk3576.c +++ b/drivers/clk/rockchip/clk-rk3576.c @@ -1594,6 +1594,8 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = { RK3576_PMU_CLKGATE_CON(4), 2, GFLAGS), GATE(PCLK_PMUPHY_ROOT, "pclk_pmuphy_root", "pclk_pmu1_root", CLK_IS_CRITICAL, RK3576_PMU_CLKGATE_CON(5), 0, GFLAGS), + GATE(PCLK_HDPTX_APB, "pclk_hdptx_apb", "pclk_pmuphy_root", 0, + RK3576_PMU_CLKGATE_CON(0), 1, GFLAGS), GATE(PCLK_MIPI_DCPHY, "pclk_mipi_dcphy", "pclk_pmuphy_root", 0, RK3576_PMU_CLKGATE_CON(0), 2, GFLAGS), GATE(PCLK_CSIDPHY, "pclk_csidphy", "pclk_pmuphy_root", 0, diff --git a/include/dt-bindings/clock/rockchip,rk3576-cru.h b/include/dt-bindings/clock/rockchip,rk3576-cru.h index 4d262a77aa1f..19d25f082dc5 100644 --- a/include/dt-bindings/clock/rockchip,rk3576-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h @@ -557,6 +557,7 @@ #define CLK_AUDIO_FRAC_1_SRC 555 #define CLK_AUDIO_FRAC_2_SRC 556 #define CLK_AUDIO_FRAC_3_SRC 557 +#define PCLK_HDPTX_APB 558 /* secure clk */ #define CLK_STIMER0_ROOT 600