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HDMI: optimize rk3288 hdmi driver code
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@@ -145,7 +145,6 @@ static int rk3288_hdmi_drv_init(struct hdmi *hdmi_drv)
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{
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int ret = 0;
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struct rk_screen screen;
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//struct rk_hdmi_device *hdmi_dev = container_of(hdmi_drv, struct rk_hdmi_device, driver);
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rk_fb_get_prmry_screen(&screen);
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hdmi_dev->lcdc_id = (screen.lcdc_id == 1) ? 0 : 1; //hdmi is extend as default,TODO modify if hdmi is primary
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@@ -180,9 +179,6 @@ static int rk3288_hdmi_parse_dt(struct rk3288_hdmi_device *hdmi_dev)
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int val = 0;
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struct device_node *np = hdmi_dev->dev->of_node;
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//if(!of_property_read_u32(np, "rockchips,hdmi_lcdc_source", &val))
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// hdmi_dev->lcdc_id = val;
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if(!of_property_read_u32(np, "rockchips,hdmi_audio_source", &val))
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hdmi_dev->driver.audio.type = val;
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@@ -53,8 +53,9 @@ static void rk3288_hdmi_set_pwr_mode(struct hdmi *hdmi_drv, int mode)
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switch(mode)
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{
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case NORMAL:
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hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ, m_TMDS_SWRST | m_PIXEL_SWRST,
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v_TMDS_SWRST(0) | v_PIXEL_SWRST(0));
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hdmi_msk_reg(hdmi_dev, A_HDCPCFG0, m_ENCRYPT_BYPASS, v_ENCRYPT_BYPASS(1)); //cfg to bypass hdcp data encry
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hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ, 0x00);
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hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ_2, 0x00);
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hdmi_msk_reg(hdmi_dev, MC_CLKDIS, m_AUDCLK_DISABLE | m_PREPCLK_DISABLE | m_TMDSCLK_DISABLE | m_PIXELCLK_DISABLE,
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v_AUDCLK_DISABLE(0) | v_PREPCLK_DISABLE(0) | v_TMDSCLK_DISABLE(0) | v_PIXELCLK_DISABLE(0));
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hdmi_msk_reg(hdmi_dev, PHY_CONF0, m_TXPWRON_SIG, v_TXPWRON_SIG(1));
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@@ -413,7 +414,7 @@ static int rk3288_hdmi_write_phy(struct rk3288_hdmi_device *hdmi_dev, int reg_ad
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hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_0, val & 0xff);
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hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_WRITE);
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i = 100;
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i = 200;
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while(i--) {
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mutex_lock(&hdmi_dev->int_mutex);
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//op_status = hdmi_readl(hdmi_dev, PHY_I2CM_INT);
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@@ -423,7 +424,7 @@ static int rk3288_hdmi_write_phy(struct rk3288_hdmi_device *hdmi_dev, int reg_ad
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if(op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR)) {
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break;
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}
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msleep(10);
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msleep(5);
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}
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if(op_status & m_I2CMPHY_DONE) {
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@@ -446,13 +447,6 @@ static int rk3288_hdmi_config_phy(struct hdmi *hdmi_drv)
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const struct phy_mpll_config_tab *phy_mpll = NULL;
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struct rk3288_hdmi_device *hdmi_dev = container_of(hdmi_drv, struct rk3288_hdmi_device, driver);
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//get phy_type,if PHY_GEN2==1 config phy register
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//phy_type = hdmi_readl(hdmi_dev, CONFIG2_ID);
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//if(phy_type != HDMI_3D_TX_WITH_HEAC_PHY && phy_type != HDMI_3D_TX_PHY) {
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// printk("%s: PHY_GEN2 = 0,No need to config phy", __FUNCTION__);
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// return;
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//}
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//hdmi_writel(hdmi_dev, PHY_CONF0, 0x32);
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hdmi_msk_reg(hdmi_dev, PHY_CONF0, m_PDDQ_SIG | m_TXPWRON_SIG, v_PDDQ_SIG(1) | v_TXPWRON_SIG(0));
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hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(1));
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@@ -462,15 +456,15 @@ static int rk3288_hdmi_config_phy(struct hdmi *hdmi_drv)
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hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(0));
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//Set slave address as PHY GEN2 address
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hdmi_writel(hdmi_dev, PHY_I2CM_SLAVE, PHY_I2C_SLAVE_ADDR); //TODO Daisen wait to modify
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hdmi_writel(hdmi_dev, PHY_I2CM_SLAVE, PHY_GEN2_ADDR); //TODO Daisen wait to modify
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#if 0
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rk3288_hdmi_write_phy(hdmi_dev, 0x13, 0x0000); /* PLLPHBYCTRL */
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rk3288_hdmi_write_phy(hdmi_dev, 0x17, 0x0006);
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/* RESISTANCE TERM 133Ohm Cfg */
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rk3288_hdmi_write_phy(hdmi_dev, 0x19, 0x0005); /* TXTERM */ //TODO Daisen wait to modify
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rk3288_hdmi_write_phy(hdmi_dev, 0x19, 0x0005); /* TXTERM */
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/* REMOVE CLK TERM */
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rk3288_hdmi_write_phy(hdmi_dev, 0x05, 0x8000); /* CKCALCTRL */
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#endif
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//config the required PHY I2C register
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phy_mpll = get_phy_mpll_tab(hdmi_drv->tmdsclk, pix_repet, 8);
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if(phy_mpll) {
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@@ -497,7 +491,8 @@ static int rk3288_hdmi_config_phy(struct hdmi *hdmi_drv)
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}
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}
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if((stat & m_PHY_LOCK) == 0) {
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hdmi_err(hdmi_dev->dev, "PHY PLL not locked\n");
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stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
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hdmi_err(hdmi_dev->dev, "PHY PLL not locked: PCLK_ON=%d,TMDSCLK_ON=%d\n", stat & m_PCLK_ON, stat & m_TMDSCLK_ON);
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return -1;
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}
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