From a6ec7c8b044ed003c531f92d3475c3b79b9db656 Mon Sep 17 00:00:00 2001 From: MingLiang Dong Date: Fri, 1 Nov 2019 15:06:56 +0800 Subject: [PATCH] hdr: default disable hdr hist module [1/1] PD#SWPL-16107 Problem: tm2 default hdr hist module enable, it cause power consumption is high. Solution: 1. default disable hdr hist module 2. if enable hdr2sdr, enable hist module Verify: verify on TM2 Change-Id: I648e9d5ac6739c1b6ef04db5ac3aec6e8f695cf7 Signed-off-by: MingLiang Dong --- .../amlogic/media/enhancement/amvecm/amcsc.c | 7 +- .../amlogic/media/enhancement/amvecm/amvecm.c | 18 +++++ .../enhancement/amvecm/arch/vpp_hdr_regs.h | 11 +++ .../media/enhancement/amvecm/set_hdr2_v0.c | 75 ++++++++++++++++--- .../media/enhancement/amvecm/set_hdr2_v0.h | 1 + 5 files changed, 97 insertions(+), 15 deletions(-) diff --git a/drivers/amlogic/media/enhancement/amvecm/amcsc.c b/drivers/amlogic/media/enhancement/amvecm/amcsc.c index 6835d8565d35..63954818ccb6 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amcsc.c +++ b/drivers/amlogic/media/enhancement/amvecm/amcsc.c @@ -7270,11 +7270,8 @@ static int vpp_matrix_update( &hdmitx_hdr10plus_params[vd_path]); if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB_DYNAMIC) || - (csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB)) { - if ((vd_path == VD1_PATH) && - (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))) - get_hist(VD1_HDR, HIST_O_BEFORE); - } + (csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB)) + get_hist(VD1_HDR, HIST_O_BEFORE); } diff --git a/drivers/amlogic/media/enhancement/amvecm/amvecm.c b/drivers/amlogic/media/enhancement/amvecm/amvecm.c index c288c7d4f427..5f7d3e3871b9 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amvecm.c +++ b/drivers/amlogic/media/enhancement/amvecm/amvecm.c @@ -6731,6 +6731,21 @@ static void def_hdr_sdr_mode(void) sdr_mode = 2; } +void hdr_hist_config_int(void) +{ + VSYNC_WR_MPEG_REG(VD1_HDR2_HIST_CTRL, 0x5510); + VSYNC_WR_MPEG_REG(VD1_HDR2_HIST_H_START_END, 0x10000); + VSYNC_WR_MPEG_REG(VD1_HDR2_HIST_V_START_END, 0x0); + + VSYNC_WR_MPEG_REG(VD2_HDR2_HIST_CTRL, 0x5510); + VSYNC_WR_MPEG_REG(VD2_HDR2_HIST_H_START_END, 0x10000); + VSYNC_WR_MPEG_REG(VD2_HDR2_HIST_V_START_END, 0x0); + + VSYNC_WR_MPEG_REG(OSD1_HDR2_HIST_CTRL, 0x5510); + VSYNC_WR_MPEG_REG(OSD1_HDR2_HIST_H_START_END, 0x10000); + VSYNC_WR_MPEG_REG(OSD1_HDR2_HIST_V_START_END, 0x0); +} + /* #if (MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV) */ void init_pq_setting(void) { @@ -6779,6 +6794,9 @@ tvchip_pq_setting: cm_init_config(bitdepth); /*lc init*/ lc_init(bitdepth); + + if (cpu_after_eq(MESON_CPU_MAJOR_ID_TM2)) + hdr_hist_config_int(); } /*probe close sr0 peaking for switch on video*/ WRITE_VPP_REG_BITS(VPP_SRSHARP0_CTRL, 1, 0, 1); diff --git a/drivers/amlogic/media/enhancement/amvecm/arch/vpp_hdr_regs.h b/drivers/amlogic/media/enhancement/amvecm/arch/vpp_hdr_regs.h index 360bc17115cd..fa65566a6882 100644 --- a/drivers/amlogic/media/enhancement/amvecm/arch/vpp_hdr_regs.h +++ b/drivers/amlogic/media/enhancement/amvecm/arch/vpp_hdr_regs.h @@ -97,6 +97,8 @@ extern struct am_regs_s r_lut_hdr_sdr_level3; #define VD1_HDR2_MATRIXI_EN_CTRL 0x383b #define VD1_HDR2_MATRIXO_EN_CTRL 0x383c #define VD1_HDR2_HIST_CTRL 0x383d +#define VD1_HDR2_HIST_H_START_END 0x383e +#define VD1_HDR2_HIST_V_START_END 0x383f #define VD2_HDR2_CTRL 0x3850 #define VD2_HDR2_CLK_GATE 0x3851 @@ -158,6 +160,9 @@ extern struct am_regs_s r_lut_hdr_sdr_level3; #define VD2_HDR2_PROC_WIN2 0x388a #define VD2_HDR2_MATRIXI_EN_CTRL 0x388b #define VD2_HDR2_MATRIXO_EN_CTRL 0x388c +#define VD2_HDR2_HIST_CTRL 0x388d +#define VD2_HDR2_HIST_H_START_END 0x388e +#define VD2_HDR2_HIST_V_START_END 0x388f #define OSD1_HDR2_CTRL 0x38a0 #define OSD1_HDR2_CLK_GATE 0x38a1 @@ -219,6 +224,9 @@ extern struct am_regs_s r_lut_hdr_sdr_level3; #define OSD1_HDR2_PROC_WIN2 0x38da #define OSD1_HDR2_MATRIXI_EN_CTRL 0x38db #define OSD1_HDR2_MATRIXO_EN_CTRL 0x38dc +#define OSD1_HDR2_HIST_CTRL 0x38dd +#define OSD1_HDR2_HIST_H_START_END 0x38de +#define OSD1_HDR2_HIST_V_START_END 0x38df #define DI_HDR2_CTRL 0x3770 #define DI_HDR2_CLK_GATE 0x3771 @@ -280,6 +288,9 @@ extern struct am_regs_s r_lut_hdr_sdr_level3; #define DI_HDR2_PROC_WIN2 0x37aa #define DI_HDR2_MATRIXI_EN_CTRL 0x37ab #define DI_HDR2_MATRIXO_EN_CTRL 0x37ac +#define DI_HDR2_HIST_CTRL 0x37ad +#define DI_HDR2_HIST_H_START_END 0x37ae +#define DI_HDR2_HIST_V_START_END 0x37af #define VDIN0_HDR2_CTRL 0x1280 #define VDIN0_HDR2_CLK_GATE 0x1281 diff --git a/drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.c b/drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.c index 35a89aa054bb..4b975243aaa6 100644 --- a/drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.c +++ b/drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.c @@ -2175,20 +2175,17 @@ void get_hist(enum hdr_module_sel module_sel, enum hdr_hist_sel hist_sel) unsigned int hist_height, hist_width, i; u32 num_pixel, total_pixel, percentile_index; - return; - if (module_sel == VD1_HDR) hist_ctrl_port = VD1_HDR2_HIST_CTRL; else return; - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { - hist_width = READ_VPP_REG_BITS(VPP_PREBLEND_H_SIZE, 0, 13); - hist_height = READ_VPP_REG_BITS(VPP_PREBLEND_H_SIZE, 16, 13); - } else { - hist_height = READ_VPP_REG_BITS(VPP_IN_H_V_SIZE, 0, 13); - hist_width = READ_VPP_REG_BITS(VPP_IN_H_V_SIZE, 16, 13); - } + if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) + return; + + hist_width = READ_VPP_REG_BITS(VPP_PREBLEND_H_SIZE, 0, 13); + hist_height = READ_VPP_REG_BITS(VPP_PREBLEND_H_SIZE, 16, 13); + if (!hist_width || !hist_height) return; @@ -2200,7 +2197,7 @@ void get_hist(enum hdr_module_sel module_sel, enum hdr_hist_sel hist_sel) return; } - for (i = 0; i < NUM_HDR_HIST; i++) + for (i = 0; i < NUM_HDR_HIST - 1; i++) memcpy(hdr_hist[i], hdr_hist[i + 1], 128 * sizeof(uint32_t)); total_pixel = 0; for (i = 0; i < 128; i++) { @@ -2226,6 +2223,7 @@ void get_hist(enum hdr_module_sel module_sel, enum hdr_hist_sel hist_sel) } } +#ifdef HDR2_PRINT if (total_pixel && percentile_index) { for (i = 0; i < 16; i++) { pr_info("hist[%d..]=%d %d %d %d %d %d %d %d\n", @@ -2245,6 +2243,49 @@ void get_hist(enum hdr_module_sel module_sel, enum hdr_hist_sel hist_sel) percentile[6]); } } +#endif +} + +void hdr_hist_config( + enum hdr_module_sel module_sel, + struct hdr_proc_lut_param_s *hdr_lut_param) +{ + unsigned int hist_ctrl; + unsigned int hist_hs_he; + unsigned int hist_vs_ve; + + if (module_sel == VD1_HDR) { + hist_ctrl = VD1_HDR2_HIST_CTRL; + hist_hs_he = VD1_HDR2_HIST_H_START_END; + hist_vs_ve = VD1_HDR2_HIST_V_START_END; + } else if (module_sel == VD2_HDR) { + hist_ctrl = VD2_HDR2_HIST_CTRL; + hist_hs_he = VD2_HDR2_HIST_H_START_END; + hist_vs_ve = VD2_HDR2_HIST_V_START_END; + } else if (module_sel == OSD1_HDR) { + hist_ctrl = OSD1_HDR2_HIST_CTRL; + hist_hs_he = OSD1_HDR2_HIST_H_START_END; + hist_vs_ve = OSD1_HDR2_HIST_V_START_END; + } else if (module_sel == DI_HDR) { + hist_ctrl = DI_HDR2_HIST_CTRL; + hist_hs_he = DI_HDR2_HIST_H_START_END; + hist_vs_ve = DI_HDR2_HIST_V_START_END; + } else { + return; + } + + if (get_cpu_type() < MESON_CPU_MAJOR_ID_TM2) + return; + + if (hdr_lut_param->hist_en) { + VSYNC_WR_MPEG_REG(hist_ctrl, 0); + VSYNC_WR_MPEG_REG(hist_hs_he, 0xeff); + VSYNC_WR_MPEG_REG(hist_vs_ve, 0x86f); + } else { + VSYNC_WR_MPEG_REG(hist_ctrl, 0x5510); + VSYNC_WR_MPEG_REG(hist_hs_he, 0x10000); + VSYNC_WR_MPEG_REG(hist_vs_ve, 0x0); + } } struct hdr_proc_lut_param_s hdr_lut_param; @@ -2348,6 +2389,7 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel, hdr_lut_param.lut_on = LUT_ON; hdr_lut_param.cgain_en = LUT_ON; } + hdr_lut_param.hist_en = LUT_OFF; } else if (hdr_process_select == RGB_HDR) { for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { hdr_lut_param.oetf_lut[i] = oe_y_lut_hdr[i]; @@ -2361,6 +2403,7 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel, hdr_lut_param.bitdepth = bit_depth; hdr_lut_param.lut_on = LUT_ON; hdr_lut_param.cgain_en = LUT_ON; + hdr_lut_param.hist_en = LUT_OFF; } else if (hdr_process_select == RGB_HLG) { for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { hdr_lut_param.oetf_lut[i] = oe_y_lut_hlg[i]; @@ -2374,6 +2417,7 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel, hdr_lut_param.lut_on = LUT_ON; hdr_lut_param.bitdepth = bit_depth; hdr_lut_param.cgain_en = LUT_ON; + hdr_lut_param.hist_en = LUT_OFF; } else if (hdr_process_select == HDR_BYPASS || hdr_process_select == HLG_BYPASS) { for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { @@ -2402,6 +2446,7 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel, hdr_lut_param.lut_on = LUT_ON; hdr_lut_param.bitdepth = bit_depth; hdr_lut_param.cgain_en = LUT_OFF; + hdr_lut_param.hist_en = LUT_ON; } else if (hdr_process_select == SDR_HDR) { for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { hdr_lut_param.oetf_lut[i] = oe_y_lut_hdr[i]; @@ -2415,6 +2460,7 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel, hdr_lut_param.lut_on = LUT_ON; hdr_lut_param.bitdepth = bit_depth; hdr_lut_param.cgain_en = LUT_ON; + hdr_lut_param.hist_en = LUT_OFF; } else if (hdr_process_select == HLG_SDR) { for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { hdr_lut_param.oetf_lut[i] = oe_y_lut_sdr[i]; @@ -2427,6 +2473,7 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel, hdr_lut_param.lut_on = LUT_ON; hdr_lut_param.bitdepth = bit_depth; hdr_lut_param.cgain_en = LUT_OFF; + hdr_lut_param.hist_en = LUT_ON; } else if (hdr_process_select == HLG_HDR) { for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { hdr_lut_param.oetf_lut[i] = oe_y_lut_hdr[i]; @@ -2439,6 +2486,7 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel, hdr_lut_param.lut_on = LUT_ON; hdr_lut_param.bitdepth = bit_depth; hdr_lut_param.cgain_en = LUT_ON; + hdr_lut_param.hist_en = LUT_ON; } else if (hdr_process_select == SDR_HLG) { for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { hdr_lut_param.oetf_lut[i] = oe_y_lut_hlg[i]; @@ -2452,6 +2500,7 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel, hdr_lut_param.lut_on = LUT_ON; hdr_lut_param.bitdepth = bit_depth; hdr_lut_param.cgain_en = LUT_OFF; + hdr_lut_param.hist_en = LUT_OFF; } else if (hdr_process_select == SDR_IPT) { for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { hdr_lut_param.oetf_lut[i] = oe_y_lut_hdr[i]; @@ -2478,6 +2527,7 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel, hdr_lut_param.lut_on = LUT_ON; hdr_lut_param.bitdepth = bit_depth; hdr_lut_param.cgain_en = LUT_ON; + hdr_lut_param.hist_en = LUT_OFF; } else if (hdr_process_select == HLG_IPT) { for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { hdr_lut_param.oetf_lut[i] = oe_y_lut_hdr[i]; @@ -2506,6 +2556,7 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel, hdr_lut_param.lut_on = LUT_ON; hdr_lut_param.bitdepth = bit_depth; hdr_lut_param.cgain_en = LUT_ON; + hdr_lut_param.hist_en = LUT_ON; } else if (hdr_process_select == HDR_IPT) { for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { hdr_lut_param.oetf_lut[i] = oe_y_lut_hdr[i]; @@ -2532,6 +2583,7 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel, hdr_lut_param.lut_on = LUT_ON; hdr_lut_param.bitdepth = bit_depth; hdr_lut_param.cgain_en = LUT_ON; + hdr_lut_param.hist_en = LUT_ON; } else if (hdr_process_select == HDR_HLG) { for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { hdr_lut_param.oetf_lut[i] = oe_y_lut_hlg[i]; @@ -2546,6 +2598,7 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel, hdr_lut_param.lut_on = LUT_ON; hdr_lut_param.bitdepth = bit_depth; hdr_lut_param.cgain_en = LUT_OFF; + hdr_lut_param.hist_en = LUT_ON; } else return hdr_process_select; #ifdef HDR2_PRINT @@ -3041,6 +3094,8 @@ enum hdr_process_sel hdr10p_func( set_c_gain(module_sel, &hdr_lut_param); + hdr_hist_config(module_sel, &hdr_lut_param); + return hdr_process_select; } diff --git a/drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.h b/drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.h index a066547725d9..2861a34e6277 100644 --- a/drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.h +++ b/drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.h @@ -148,6 +148,7 @@ struct hdr_proc_lut_param_s { unsigned int lut_on; unsigned int bitdepth; unsigned int cgain_en; + unsigned int hist_en; }; typedef int64_t(*MenuFun)(int64_t);