From a6f921d31f907d12c62636dfd7116c24ad1feffe Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Tue, 29 Jun 2021 08:38:42 +0800 Subject: [PATCH] mmc: dw_mmc-rockchip: Always fix ID mode clk request into 375KHz for RK356X RK356X SoCs only support 375KHz for ID mode, otherwise it will be always failed to set clk if the first attempt to identify cards. Signed-off-by: Shawn Lin Change-Id: I99ba322b3eeb4c4658869dc88b7a9f303081e12e --- drivers/mmc/host/dw_mmc-rockchip.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index 1e4739e3f2e1..cc7cd5e7fd21 100644 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -28,6 +28,7 @@ struct dw_mci_rockchip_priv_data { int num_phases; bool use_v2_tuning; int last_degree; + u32 f_min; }; static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) @@ -49,6 +50,9 @@ static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) * Note: div can only be 0 or 1, but div must be set to 1 for eMMC * DDR52 8-bit mode. */ + if (ios->clock < priv->f_min) + ios->clock = priv->f_min; + if (ios->bus_width == MMC_BUS_WIDTH_8 && ios->timing == MMC_TIMING_MMC_DDR52) cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV; @@ -316,6 +320,17 @@ static int dw_mci_rk3288_parse_dt(struct dw_mci *host) if (!priv) return -ENOMEM; + /* + * RK356X SoCs only support 375KHz for ID mode, so any clk request + * that less than 1.6MHz(2 * 400KHz * RK3288_CLKGEN_DIV) should be + * wrapped into 375KHz + */ + if (of_device_is_compatible(host->dev->of_node, + "rockchip,rk3568-dw-mshc")) + priv->f_min = 375000; + else + priv->f_min = 100000; + if (of_property_read_u32(np, "rockchip,desired-num-phases", &priv->num_phases)) priv->num_phases = 360;