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BACKPORT: serial: 8250_bcm7271: improve bcm7271 8250 port

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The 8250 BCM7271 UART is not a direct match to PORT_16550A and other
generic ports do not match its hardware capabilities. PORT_ALTR matches
the rx trigger levels, but its vendor configurations are not compatible.
Unfortunately this means we need to create another port to fully capture
the hardware capabilities of the BCM7271 UART.

To alleviate some latency pressures, we default the rx trigger level to 8.

Bug: 365149220
Change-Id: I41005a210439a3a54a9af16a96583662dc8d786d
Signed-off-by: Justin Chen <justin.chen@broadcom.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Acked-by: Doug Berger <opendmb@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/1692643978-16570-1-git-send-email-justin.chen@broadcom.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 42a569cd0d)
Signed-off-by: Danesh Petigara <danesh.petigara@broadcom.com>
This commit is contained in:
Justin Chen
2023-08-21 11:52:51 -07:00
committed by Pierre Couillaud
parent 04212acc42
commit a752cdd96f
3 changed files with 12 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/tty/serial/8250/8250_bcm7271.c
View File

@@ -1059,7 +1059,7 @@ static int brcmuart_probe(struct platform_device *pdev)
dev_dbg(dev, "DMA is %senabled\n", priv->dma_enabled ? "" : "not ");
memset(&up, 0, sizeof(up));
up.port.type = PORT_16550A;
up.port.type = PORT_BCM7271;
up.port.uartclk = clk_rate;
up.port.dev = dev;
up.port.mapbase = mapbase;
@@ -1073,8 +1073,6 @@ static int brcmuart_probe(struct platform_device *pdev)
| UPF_FIXED_PORT | UPF_FIXED_TYPE;
up.port.dev = dev;
up.port.private_data = priv;
up.capabilities = UART_CAP_FIFO | UART_CAP_AFE;
up.port.fifosize = 32;
/* Check for a fixed line number */
ret = of_alias_get_id(np, "serial");

8
drivers/tty/serial/8250/8250_port.c
View File

@@ -314,6 +314,14 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {1, 4, 8, 14},
.flags = UART_CAP_FIFO,
},
[PORT_BCM7271] = {
.name = "Broadcom BCM7271 UART",
.fifo_size = 32,
.tx_loadsz = 32,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
.rxtrig_bytes = {1, 8, 16, 30},
.flags = UART_CAP_FIFO | UART_CAP_AFE,
},
};
/* Uart divisor latch read */

3
include/uapi/linux/serial_core.h
View File

@@ -144,6 +144,9 @@
/* Blackfin bf5xx */
#define PORT_BFIN 75
/* Broadcom BCM7271 UART */
#define PORT_BCM7271 76
/* Broadcom SB1250, etc. SOC */
#define PORT_SB1250_DUART 77