diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 62c9b9db7cf0..316bf6054fa1 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -843,12 +843,14 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rv1108-evb.dtb \
 	rv1109-evb-ddr3-v10.dtb \
+	rv1109-evb-ddr3-v12.dtb \
 	rv1109-evb-lp3-v10.dtb \
 	rv1109-fpga.dtb \
 	rv1126-ai-cam-ddr3-v1.dtb \
 	rv1126-evb-ddr3-v10.dtb \
 	rv1126-evb-ddr3-v10-spi-nand.dtb \
 	rv1126-evb-ddr3-v10-tb.dtb \
+	rv1126-evb-ddr3-v12.dtb \
 	rv1126-evb-lp3-v10.dtb \
 	rv1126-iotest-v10.dtb \
 	rv1126-ipc2-ddr3-v10.dtb \
diff --git a/arch/arm/boot/dts/rv1109-evb-ddr3-v12.dts b/arch/arm/boot/dts/rv1109-evb-ddr3-v12.dts
new file mode 100644
index 000000000000..3355d42e5440
--- /dev/null
+++ b/arch/arm/boot/dts/rv1109-evb-ddr3-v12.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ */
+/dts-v1/;
+#include "rv1109.dtsi"
+#include "rv11xx-evb-v12.dtsi"
+/ {
+	model = "Rockchip RV1109 EVB DDR3 Board";
+	compatible = "rockchip,rv1109-evb-ddr3-v12", "rockchip,rv1109";
+
+	chosen {
+		bootargs = "earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait snd_aloop.index=7";
+	};
+};
diff --git a/arch/arm/boot/dts/rv1126-evb-ddr3-v12.dts b/arch/arm/boot/dts/rv1126-evb-ddr3-v12.dts
new file mode 100644
index 000000000000..28d50b2bb93f
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-evb-ddr3-v12.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ */
+/dts-v1/;
+#include "rv1126.dtsi"
+#include "rv11xx-evb-v12.dtsi"
+/ {
+	model = "Rockchip RV1126 EVB DDR3 Board";
+	compatible = "rockchip,rv1126-evb-ddr3-v12", "rockchip,rv1126";
+
+	chosen {
+		bootargs = "earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait snd_aloop.index=7";
+	};
+};
diff --git a/arch/arm/boot/dts/rv11xx-evb-v12.dtsi b/arch/arm/boot/dts/rv11xx-evb-v12.dtsi
new file mode 100644
index 000000000000..521cb8fa21a4
--- /dev/null
+++ b/arch/arm/boot/dts/rv11xx-evb-v12.dtsi
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ */
+
+#include "rv11xx-evb-v10.dtsi"
+/ {
+	/delete-node/ vdd-npu;
+	/delete-node/ vdd-vepu;
+
+	vdd_logic: vdd-logic {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_logic";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <810000>;
+		regulator-max-microvolt = <810000>;
+	};
+};
+
+&rk809 {
+	regulators {
+		/delete-node/ DCDC_REG1;
+		vdd_npu_vepu: DCDC_REG1 {
+			regulator-always-on;
+			regulator-boot-on;
+			regulator-min-microvolt = <650000>;
+			regulator-max-microvolt = <950000>;
+			regulator-ramp-delay = <6001>;
+			regulator-initial-mode = <0x2>;
+			regulator-name = "vdd_npu_vepu";
+			regulator-state-mem {
+				regulator-off-in-suspend;
+			};
+		};
+	};
+};
+
+&ov4689 {
+	reset-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
+};
+
+&os04a10 {
+	reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
+};
+
+&npu {
+	npu-supply = <&vdd_npu_vepu>;
+};
+
+&pwm0 {
+	status = "disabled";
+};
+
+&pwm1 {
+	status = "disabled";
+};
+
+&rkvenc {
+	venc-supply = <&vdd_npu_vepu>;
+};