From a7ee710147ec49ddf28f7bd8c0a37a74c1b87ead Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Wed, 5 Mar 2025 16:29:54 +0800 Subject: [PATCH] phy: rockchip: naneng-combphy: Configuring grf with clk enabled Change-Id: Ie6c2e5dcd9936ff8e65783faee72ef55a8dce4d2 Signed-off-by: Jon Lin --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 2daa3a688ee0..8ed9a6c7cc33 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -367,6 +367,13 @@ static int rockchip_combphy_parse_dt(struct device *dev, return PTR_ERR(priv->phy_grf); } + /* Configuring grf with cru enabled. */ + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) { + dev_err(priv->dev, "failed to enable clocks\n"); + return ret; + } + if (device_property_present(dev, "rockchip,dis-u3otg0-port")) { rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg0_port_en, false); @@ -388,6 +395,8 @@ static int rockchip_combphy_parse_dt(struct device *dev, regmap_write(priv->pipe_grf, vals[0], (GENMASK(vals[2], vals[1]) << 16) | (vals[3] << vals[1])); + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + priv->apb_rst = devm_reset_control_get_optional(dev, "combphy-apb"); if (IS_ERR(priv->apb_rst)) { ret = PTR_ERR(priv->apb_rst);