From a80efcc59cec34e38b20786c8b4e22e02f7a404a Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Fri, 25 Feb 2022 09:18:13 +0800 Subject: [PATCH] clk: rockchip: link: Add pclk_vo0_grf clock Signed-off-by: Wyon Bi Change-Id: I321e5dbcb4fd32f41ac85d284e511bc8ad1ed789 --- drivers/clk/rockchip/clk-link.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-link.c b/drivers/clk/rockchip/clk-link.c index 59dd6535d18c..be59fa53da8a 100644 --- a/drivers/clk/rockchip/clk-link.c +++ b/drivers/clk/rockchip/clk-link.c @@ -95,6 +95,7 @@ static const struct rockchip_link_info rk3588_clk_gate_link_info[] = { GATE_LINK("aclk_av1_pre", "aclk_av1_root", 1), GATE_LINK("pclk_av1_pre", "pclk_av1_root", 4), GATE_LINK("hclk_sdio_pre", "hclk_sdio_root", 1), + GATE_LINK("pclk_vo0_grf", "pclk_vo0_root", 10), }; static const struct rockchip_link rk3588_clk_gate_link = {