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HDMI: init rk3288 hdmi driver code

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This commit is contained in:
zwl
2014-03-04 09:53:36 +08:00
parent 819e39a55b
commit a8141dcd8c
5 changed files with 737 additions and 0 deletions
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8
drivers/video/rockchip/hdmi/chips/rk3288/Makefile Normal file
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#
# Makefile for HDMI linux kernel module.
#
ccflags-$(CONFIG_RK_HDMI_DEBUG) = -DDEBUG -DHDMI_DEBUG
obj-$(CONFIG_HDMI_RK3288) += rk3288_hdmi_hw.o rk3288_hdmi.o
obj-$(CONFIG_HDCP_RK3288) += hdcp/

52
drivers/video/rockchip/hdmi/chips/rk3288/rk3288_hdmi.c Normal file
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#include "rk3288_hdmi_hw.h"
#include "rk3288_hdmi.h"
#if defined(CONFIG_OF)
static const struct of_device_id rk3288_hdmi_dt_ids[] = {
{.compatible = "rockchips,rk3288-hdmi",},
{}
};
MODULE_DEVICE_TABLE(of, rk3288_hdmi_dt_ids);
#endif
static int rk3288_hdmi_probe (struct platform_device *pdev)
{
return 0;
}
static int rk3288_hdmi_remove(struct platform_device *pdev)
{
return 0;
}
static void rk3288_hdmi_shutdown(struct platform_device *pdev)
{
}
static struct platform_driver rk3288_hdmi_driver = {
.probe = rk3288_hdmi_probe,
.remove = rk3288_hdmi_remove,
.driver = {
.name = "rk3288-hdmi",
.owner = THIS_MODULE,
.of_match_table = of_match_ptr(rk3288_hdmi_dt_ids),
},
.shutdown = rk30_hdmi_shutdown,
};
static int __init rk3288_hdmi_init(void)
{
return platform_driver_register(&rk3288_hdmi_driver);
}
static void __exit rk3288_hdmi_exit(void)
{
platform_driver_unregister(&rk3288_hdmi_driver);
}
device_initcall_sync(rk3288_hdmi_init);
module_exit(rk3288_hdmi_exit);

29
drivers/video/rockchip/hdmi/chips/rk3288/rk3288_hdmi.h Normal file
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#ifndef __RK3288_HDMI_H__
#define __RK3288_HDMI_H__
#include "../../rk_hdmi.h"
#if defined(CONFIG_HDMI_SOURCE_LCDC1)
#define HDMI_SOURCE_DEFAULT HDMI_SOURCE_LCDC1
#else
#define HDMI_SOURCE_DEFAULT HDMI_SOURCE_LCDC0
#endif
enum{
INPUT_IIS,
INPUT_SPDIF
};
#if defined(CONFIG_SND_RK_SOC_HDMI_SPDIF)
#define HDMI_CODEC_SOURCE_SELECT INPUT_SPDIF
#else
#define HDMI_CODEC_SOURCE_SELECT INPUT_IIS
#endif
struct rk_hdmi_device {
struct rk_hdmi_driver hdmi_drv;
struct delayed_work hdmi_delay_work;
struct work_struct hdmi_irq_work_struct;
struct dentry *debugfs_dir;
};
#endif /* __RK3288_HDMI_H__ */

42
drivers/video/rockchip/hdmi/chips/rk3288/rk3288_hdmi_hw.c Normal file
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#include "rk3288_hdmi_hw.h"
int rk3288_hdmi_detect_hotplug(struct hdmi *hdmi_drv)
{
return 0;
}
int rk3288_hdmi_read_edid(struct hdmi *hdmi_drv, int block, unsigned char *buff)
{
return 0;
}
int rk3288_hdmi_config_video(struct hdmi *hdmi_drv)
{
return 0;
}
int rk3288_hdmi_config_audio(struct hdmi *hdmi_drv)
{
return 0;
}
void rk3288_hdmi_control_output(struct hdmi *hdmi_drv, int enable)
{
return 0;
}
int rk3288_hdmi_initial(struct hdmi *hdmi_drv)
{
int rc = HDMI_ERROR_SUCESS;
hdmi_drv->remove = rk3288_hdmi_removed ;
hdmi_drv->control_output = rk3288_hdmi_control_output;
hdmi_drv->config_video = rk3288_hdmi_config_video;
hdmi_drv->config_audio = rk3288_hdmi_config_audio;
hdmi_drv->detect_hotplug = rk3288_hdmi_detect_hotplug;
hdmi_drv->read_edid = rk3288_hdmi_read_edid;
return rc;
}

606
drivers/video/rockchip/hdmi/chips/rk3288/rk3288_hdmi_hw.h Normal file
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#ifndef _RK3288_HDMI_HW_H
#define _RK3288_HDMI_HW_H
enum PWR_MODE{
NORMAL,
LOWER_PWR,
};
enum {
OUTPUT_DVI = 0,
OUTPUT_HDMI,
};
#define HDMI_SCL_RATE (100*1000)
/*Register and Field Descriptions*/
/*Identification Registers*/
#define IDENTIFICATION_BASE 0x0000
enum IDENTIFICATION_REG{
DESIGN_ID = IDENTIFICATION_BASE,
REVISION_ID,
PRODUCT_ID0,
PRODUCT_ID1,
CONFIG0_ID,
CONFIG1_ID,
CONFIG2_ID,
CONFIG3_ID
};
//CONFIG0_ID
#define m_PREPEN (1 << 7)
#define m_AUDSPDIF (1 << 5)
#define m_AUDI2S (1 << 4)
#define m_HDMI14 (1 << 3)
#define m_CSC (1 << 2)
#define m_CEC (1 << 1)
#define m_HDCP (1 << 0)
//CONFIG1_ID
#define m_HDMI20 (1 << 5)
#define m_CONFAPB (1 << 1)
//CONFIG2_ID
enum PHYTYPE {
HDMI_TX_PHY = 0x00,
MHL_WITH_HEAC_PHY = 0xb2,
MHL_PHY = 0xc2,
HDMI_3D_TX_WITH_HEAC_PHY = 0xe2,
HDMI_3D_TX_PHY = 0xf2
};
//CONFIG3_ID
#define m_AHB_AUD_DMA (1 << 1)
#define m_GP_AUD (1 << 0)
/*Interrupt Registers*/
#define INTERRUPT_BASE 0x0100
enum INTERRUPT_REG {
IH_FC_STAT0 = INTERRUPT_BASE,
IH_FC_STAT1,
IH_FC_STAT2,
IH_AS_STAT0,
IH_PHY_STAT0,
IH_I2CM_STAT0,
IH_CEC_STAT0,
IH_VP_STAT0,
IH_I2CMPHY_STAT0,
IH_AHBDMAAUD_STAT0,
IH_DECODE = 0x0170,
IH_MUTE_FC_STAT0 = 0x0180,
IH_MUTE_FC_STAT1,
IH_MUTE_FC_STAT2,
IH_MUTE_AS_STAT0,
IH_MUTE_PHY_STAT0,
IH_MUTE_I2CM_STAT0,
IH_MUTE_CEC_STAT0,
IH_MUTE_VP_STAT0,
IH_MUTE_I2CMPHY_STAT0,
IH_MUTE_AHBDMAAUD_STAT0,
IH_MUTE = 0x1ff
};
//IH_FC_STAT0
#define m_AUD_INFOFRAME (1 << 7)
#define m_AUD_CONTENT_PROTECT (1 << 6)
#define m_AUD_HBR (1 << 5)
#define m_AUD_SAMPLE (1 << 2)
#define m_AUD_CLK_REGEN (1 << 1)
#define m_NULL_PACKET (1 << 0)
//IH_FC_STAT1
#define m_GMD (1 << 7)
#define m_ISCR1 (1 << 6)
#define m_ISCR2 (1 << 5)
#define m_VSD (1 << 4)
#define m_SPD (1 << 3)
#define m_AVI_INFOFRAME (1 << 1)
#define m_GCP (1 << 0)
//IH_FC_STAT2
#define m_LOWPRIO_OVERFLOW (1 << 1)
#define m_HIGHPRIO_OVERFLOW (1 << 0)
//IH_AS_SATA0
#define m_FIFO_UNDERRUN (1 << 4)
#define m_FIFO_OVERRUN (1 << 3)
#define m_AUD_FIFO_UDFLOW_THR (1 << 2)
#define m_AUD_FIFO_UDFLOW (1 << 1)
#define m_AUD_FIFO_OVERFLOW (1 << 0)
//IH_PHY_STAT0
#define m_RX_SENSE3 (1 << 5)
#define m_RX_SENSE2 (1 << 4)
#define m_RX_SENSE1 (1 << 3)
#define m_RX_SENSE0 (1 << 2)
#define m_TX_PHY_LOCK (1 << 1)
#define m_HPD (1 << 0)
//IH_I2CM_STAT0
#define m_SCDC_READREQ (1 << 2)
#define m_I2CM_DONE (1 << 1)
#define m_I2CM_ERROR (1 << 0)
//IH_CEC_STAT0
#define m_WAKEUP (1 << 6)
#define m_ERR_FOLLOW (1 << 5)
#define m_ERR_INITIATOR (1 << 4)
#define m_ARB_LOST (1 << 3)
#define m_NACK (1 << 2)
#define m_EOM (1 << 1)
#define m_DONE (1 << 0)
//IH_VP_STAT0
#define m_FIFOFULL_REPET (1 << 7)
#define m_FIFOEMPTY_REPET (1 << 6)
#define m_FIFOFULL_PACK (1 << 5)
#define m_FIFOEMPTY_PACK (1 << 4)
#define m_FIFOFULL_REMAP (1 << 3)
#define m_FIFOEMPTY_REMAP (1 << 2)
#define m_FIFOFULL_BYPASS (1 << 1)
#define m_FIFOEMPTY_BYPASS (1 << 0)
//IH_I2CMPHY_STAT0
#define m_I2CMPHY_DONE (1 << 1)
#define m_I2CMPHY_ERR (1 << 0)
//IH_AHBDMAAUD_STAT0
#define m_AUDDMA_INT_BUFOVERRUN (1 << 6)
#define m_AUDDMA_INT_ERR (1 << 5)
#define m_AUDDMA_INT_LOST (1 << 4)
#define m_AUDDMA_INT_RETRYSPLIT (1 << 3)
#define m_AUDDMA_INT_DONE (1 << 2)
#define m_AUDDMA_INT_BUFFULL (1 << 1)
#define m_AUDDMA_INT_BUFEMPTY (1 << 0)
//IH_DECODE
#define m_IH_FC_STAT0 (1 << 7)
#define m_IH_FC_STAT1 (1 << 6)
#define m_IH_FC_STAT2_VP (1 << 5)
#define m_IH_AS_STAT0 (1 << 4)
#define m_IH_PHY (1 << 3)
#define m_IH_I2CM_STAT0 (1 << 2)
#define m_IH_CEC_STAT0 (1 << 1)
#define m_IH_AHBDMAAUD_STAT0 (1 << 0)
//IH_MUTE_FC_STAT0
#define m_AUDI_MUTE (1 << 7)
#define m_ACP_MUTE (1 << 6)
#define m_DST_MUTE (1 << 4)
#define m_OBA_MUTE (1 << 3)
#define m_AUDS_MUTE (1 << 2)
#define m_ACR_MUTE (1 << 1)
#define m_NULL_MUTE (1 << 0)
//Ih_MUTE_FC_STAT1
#define m_GMD_MUTE (1 << 7)
#define m_ISCR1_MUTE (1 << 6)
#define m_ISCR2_MUTE (1 << 5)
#define m_VSD_MUTE (1 << 4)
#define m_SPD_MUTE (1 << 3)
#define m_AVI_MUTE (1 << 1)
#define m_GCP_MUTE (1 << 0)
/*Video Sampler Registers*/
#define VIDEO_SAMPLER_BASE 0x0200
enum {
TX_INVID0 = VIDEO_SAMPLER_BASE,
TX_INSTUFFING,
TX_GYDATA0,
TX_GYDATA1,
TX_RCRDATA0,
TX_RCRDATA1,
TX_BCBDATA0,
TX_BCBDATA1
};
/*Video Packetizer Registers*/
#define VIDEO_PACKETIZER_BASE 0x0800
enum {
VP_STATUS = VIDEO_PACKETIZER_BASE,
VP_PR_CD,
VP_STUFF,
VP_REMAP,
VP_CONF,
VP_MASK = 0x0807
};
/*Frame Composer Registers*/
#define FRAME_COMPOSER_BASE 0x1000
enum {
FC_INVIDCONF = FRAME_COMPOSER_BASE,
FC_INHACTIV0,
FC_INHACTIV1,
FC_INHBLANK0,
FC_INHBLANK1,
FC_INVACTIV0,
FC_INVACTIV1,
FC_INVBLANK,
FC_HSYNCINDELAY0,
FC_HSYNCINDELAY1,
FC_HSYNCINWIDTH0,
FC_HSYNCINWIDTH1,
FC_VSYNCINDELAY,
FC_VSYNCINWIDTH,
FC_INFREQ0,
FC_INFREQ1,
FC_INFREQ2,
FC_CTRLDUR,
FC_EXCTRLDUR,
FC_EXCTRLSPAC,
FC_CH0PREAM,
FC_CH1PREAM,
FC_CH2PREAM,
FC_AVICONF3,
FC_GCP,
FC_AVICONF0,
FC_AVICONF1,
FC_AVICONF2,
FC_AVIVID,
FC_AVIETB0,
FC_AVIETB1,
FC_AVISBB0,
FC_AVISBB1,
FC_AVIELB0,
FC_AVIELB1,
FC_AVISRB0,
FC_AVISRB1,
FC_AUDICONF0,
FC_AUDICONF1,
FC_AUDICONF2,
FC_AUDICONF3,
FC_VSDIEEEID2,
FC_VSDSIZE,
FC_VSDIEEEID1
FC_VSDIEEEID0,
FC_VSDPAYLOAD0 = 0x1032, //0~23
FC_SPDVENDORNAME0 = 0x104a, //0~7
FC_SPDPRODUCTNAME0 = 0x1052, //0~15
FC_SPDDEVICEINF = 0x1062,
FC_AUDSCONF,
FC_AUDSSTAT,
FC_AUDSV,
FC_AUDSU,
FC_AUDSCHNLS0, //0~8
FC_CTRLQHIGH = 0x1073,
FC_CTRLQLOW,
FC_ACP0,
FC_ACP16 = 0x1082, //16~1
FC_ISCR1_0 = 0x1092,
FC_ISCR1_16, //16~1
FC_ISCR2_15 = 0x10a3, //15~0
FC_DATAUTO0 = 0x10B3,
FC_DATAUTO1,
FC_DATAUTO2,
FC_DATMAN,
FC_DATAUTO3,
FC_RDRB0,
FC_RDRB1,
FC_RDRB2,
FC_RDRB3,
FC_RDRB4,
FC_RDRB5,
FC_RDRB6,
FC_RDRB7,
FC_MASK0 = 0x10d2,
FC_MASK1 = 0x10d6,
FC_MASK2 = 0x10da,
FC_PRCONF = 0x10e0,
FC_SCRAMBLER_CTRL,
FC_GMD_STAT,
FC_GMD_EN,
FC_GMD_UP,
FC_GMD_CONF,
FC_GMD_HB,
FC_GMD_PB0, //0~27
FC_DBGFORCE = 0x1200,
FC_DBGAUD0CH0, //aud0~aud2 ch0
FC_DBGAUD0CH1 = 0x1204, //aud0~aud2 ch1
FC_DBGAUD0CH2 = 0x1207, //aud0~aud2 ch2
FC_DBGAUD0CH3 = 0x120a, //aud0~aud2 ch3
FC_DBGAUD0CH4 = 0x120d, //aud0~aud2 ch4
FC_DBGAUD0CH5 = 0x1210, //aud0~aud2 ch5
FC_DBGAUD0CH6 = 0x1213, //aud0~aud2 ch6
FC_DBGAUD0CH7 = 0x1216, //aud0~aud2 ch7
FC_DBGTMDS0 = 0x1219,
FC_DBGTMDS1,
FC_DBGTMDS2
};
/*HDMI Source PHY Registers*/
#define HDMI_SOURCE_PHY_BASE 0x3000
enum {
PHY_CONF0 = HDMI_SOURCE_PHY_BASE,
PHY_TST0,
PHY_TST1,
PHY_TST2,
PHY_STAT0,
PHY_INT0,
PHY_MASK0,
PHY_POL0,
PHY_PCLFREQ0,
PHY_PCLFREQ1,
PHY_PLLCFGFREQ0,
PHY_PLLCFGFREQ1,
PHY_PLLCFGFREQ2
};
/*I2C Master PHY Registers*/
#define I2C_MASTER_PHY_BASE 0x3020
enum {
PHY_I2CM_SLAVE = I2C_MASTER_PHY_BASE,
PHY_I2CM_ADDRESS,
PHY_I2CM_DATAO_1,
PHY_I2CM_DATAO_0,
PHY_I2CM_DATAI_1,
PHY_I2CM_DATAI_0,
PHY_I2CM_OPERATION,
PHY_I2CM_INT,
PHY_I2CM_CTLINT,
PHY_I2CM_DIV,
PHY_I2CM_SOFTRSTZ,
PHY_I2CM_SS_SCL_HCNT_1_ADDR,
PHY_I2CM_SS_SCL_HCNT_0_ADDR,
PHY_I2CM_SS_SCL_LCNT_1_ADDR,
PHY_I2CM_SS_SCL_LCNT_0_ADDR,
PHY_I2CM_FS_SCL_HCNT_1_ADDR,
PHY_I2CM_FS_SCL_HCNT_0_ADDR,
PHY_I2CM_FS_SCL_LCNT_1_ADDR,
PHY_I2CM_FS_SCL_LCNT_0_ADDR,
I2CM_PHY_SDA_HOLD
};
/*Audio Sampler Registers*/
#define AUDIO_SAMPLER_BASE 0x3100
enum {
AUD_CONF0 = AUDIO_SAMPLER_BASE,
AUD_CONF1,
AUD_INT,
AUD_CONF2,
AUD_INT1,
AUD_N1 = 0x3200,
AUD_N2,
AUD_N3,
AUD_CTS1,
AUD_CTS2,
AUD_CTS3,
AUD_INPUTCLKFS,
AUD_SPDIF0 = 0x3300,
AUD_SPDIF1,
AUD_SPDIFINT,
AUD_SPDIFINT1
};
/*Generic Parallel Audio Interface Registers*/
#define GP_AUDIO_INTERFACE_BASE 0x3500
enum {
GP_CONF0 = GP_AUDIO_INTERFACE_BASE,
GP_CONF1,
GP_CONF2,
GP_MASK = 0x3506
};
/*Audio DMA Registers*/
#define AUDIO_DMA_BASE 0x3600
enum {
AHB_DMA_CONF0 = AUDIO_DMA_BASE,
AHB_DMA_START,
AHB_DMA_STOP,
AHB_DMA_THRSLD,
AHB_DMA_STRADDR_SET0_0, //0~3
AHB_DMA_STPADDR_SET0_0 = 0x3608,//0~3
AHB_DMA_BSTADDR0 = 0x360c, //0~3
AHB_DMA_MBLENGTH0 = 0x3610, //0~3,
AHB_DMA_MASK = 0x3614,
AHB_DMA_CONF1 = 0x3616,
AHB_DMA_BUFFMASK = 0x3619,
AHB_DMA_MASK1 = 0x361b,
AHB_DMA_STATUS,
AHB_DMA_CONF2,
AHB_DMA_STRADDR_SET1_0 = 0x3620,//0~3
AHB_DMA_STPADDR_SET1_0 = 0x3624 //0~3
};
/*Main Controller Registers*/
#define MAIN_CONTROLLER_BASE 0X4000
enum {
MC_CLKDIS = 0x4001,
MC_SWRSTZREQ,
MC_OPCTRL,
MC_FLOWCTRL,
MC_PHYRSTZ,
MC_LOCKONCLOCK,
MC_HEACPHY_RST,
MC_LOCKONCLOCK2,
MC_SWRSTZREQ_2
};
/*Color Space Converter Registers*/
#define COLOR_SPACE_CONVERTER_BASE 0x4100
enum {
CSC_CFG = COLOR_SPACE_CONVERTER_BASE,
CSC_SCALE,
CSC_COEF_A1_MSB
CSC_COEF_A1_LSB,
CSC_COEF_A2_MSB,
CSC_COEF_A2_LSB,
CSC_COEF_A3_MSB,
CSC_COEF_A3_LSB,
CSC_COEF_A4_MSB,
CSC_COEF_A4_LSB,
CSC_COEF_B1_MSB,
CSC_COEF_B1_LSB,
CSC_COEF_B2_MSB,
CSC_COEF_B2_LSB,
CSC_COEF_B3_MSB,
CSC_COEF_B3_LSB,
CSC_COEF_B4_MSB,
CSC_COEF_B4_LSB,
CSC_COEF_C1_MSB,
CSC_COEF_C1_LSB,
CSC_COEF_C2_MSB,
CSC_COEF_C2_LSB,
CSC_COEF_C3_MSB,
CSC_COEF_C3_LSB,
CSC_COEF_C4_MSB,
CSC_COEF_C4_LSB,
CSC_SPARE_1,
CSC_SPARE_2
};
/*HDCP Encryption Engine Registers*/
#define HDCP_ENCRYPTION_ENGINE_BASE 0x5000
enum {
A_HDCPCFG0 = HDCP_ENCRYPTION_ENGINE_BASE,
A_HDCPCFG1,
A_HDCPOBS0,
A_HDCPOBS1,
A_HDCPOBS2,
A_HDCPOBS3,
A_APIINTCLR,
A_APIINTSTAT,
A_APIINTMSK,
A_VIDPOLCFG,
A_OESSWCFG,
A_COREVERLSB = 0x5014,
A_COREVERMSB,
A_KSVMEMCTRL,
HDCP_BSTATUS_0 = 0x5020,
HDCP_BSTATUS_1,
HDCP_M0_0,
HDCP_M0_1,
HDCP_M0_2,
HDCP_M0_3,
HDCP_M0_4,
HDCP_M0_5,
HDCP_M0_6,
HDCP_M0_7,
HDCP_KSV, //0~634
HDCP_VH = 0x52a5, //0~19
HDCP_REVOC_SIZE_0 = 0x52b9,
HDCP_REVOC_SIZE_1,
HDCP_REVOC_LIST, //0~5059
};
/*HDCP BKSV Registers*/
#define HDCP_BKSV_BASE 0x7800
enum {
HDCPREG_BKSV0 = HDCP_BKSV_BASE,
HDCPREG_BKSV1,
HDCPREG_BKSV2,
HDCPREG_BKSV3,
HDCPREG_BKSV4
};
/*HDCP AN Registers*/
#define HDCP_AN_BASE 0x7805
enum {
HDCPREG_ANCONF = HDCP_AN_BASE,
HDCPREG_AN0,
HDCPREG_AN1,
HDCPREG_AN2,
HDCPREG_AN3,
HDCPREG_AN4,
HDCPREG_AN5,
HDCPREG_AN6,
HDCPREG_AN7
};
/*Encrypted DPK Embedded Storage Registers*/
#define ENCRYPTED_DPK_EMBEDDED_BASE 0x780e
enum {
HDCPREG_RMCTL = ENCRYPTED_DPK_EMBEDDED_BASE,
HDCPREG_RMSTS,
HDCPREG_SEED0,
HDCPREG_SEED1,
HDCPREG_DPK0,
HDCPREG_DPK1,
HDCPREG_DPK2,
HDCPREG_DPK3,
HDCPREG_DPK4,
HDCPREG_DPK5,
HDCPREG_DPK6
};
/*CEC Engine Registers*/
#define CEC_ENGINE_BASE 0x7d00
enum {
CEC_CTRL = CEC_ENGINE_BASE,
CEC_MASK = 0x7d02,
CEC_ADDR_L = 0x7d05,
CEC_ADDR_H,
CEC_TX_CNT,
CEC_RX_CNT,
CEC_TX_DATA0 = 0x7d10, //txdata0~txdata15
CEC_RX_DATA0 = 0x7d20, //rxdata0~rxdata15
CEC_LOCK = 0x7d30,
CEC_WKUPCTRL
};
/*I2C Master Registers*/
#define I2C_MASTER_BASE 0x7e00
enum {
I2CM_SLAVE = I2C_MASTER_BASE,
I2CM_ADDRESS,
I2CM_DATAO,
I2CM_DATAI,
I2CM_OPERATION,
I2CM_INT,
I2CM_CTLINT,
I2CM_DIV,
I2CM_SEGADDR,
I2CM_SOFTRSTZ,
I2CM_SEGPTR,
I2CM_SS_SCL_HCNT_1_ADDR,
I2CM_SS_SCL_HCNT_0_ADDR,
I2CM_SS_SCL_LCNT_1_ADDR,
I2CM_SS_SCL_LCNT_0_ADDR,
I2CM_FS_SCL_HCNT_1_ADDR,
I2CM_FS_SCL_HCNT_0_ADDR,
I2CM_FS_SCL_LCNT_1_ADDR,
I2CM_FS_SCL_LCNT_0_ADDR,
I2CM_SDA_HOLD,
I2CM_SCDC_READ_UPDATE,
I2CM_READ_BUFF0 = 0x7e20, //buff0~buff7
I2CM_SCDC_UPDATE0 = 0x7e30,
I2CM_SCDC_UPDATE1
};
extern struct hdmi *hdmi;
static inline int hdmi_readl(u16 offset, u32 *val)
{
int ret = 0;
*val = readl_relaxed(hdmi->regbase + (offset) * 0x04);
return ret;
}
static inline int hdmi_writel(u16 offset, u32 val)
{
int ret = 0;
writel_relaxed(val, hdmi->regbase + (offset) * 0x04);
return ret;
}
static inline int hdmi_msk_reg(u16 offset, u32 msk, u32 val)
{
int ret = 0;
u32 temp;
temp = readl_relaxed(hdmi->regbase + (offset) * 0x04) & (0xFF - (msk));
writel_relaxed(temp | ( (val) & (msk) ), hdmi->regbase + (offset) * 0x04);
return ret;
}
static inline void rk3028_hdmi_reset_pclk(void)
{
writel_relaxed(0x00010001,RK2928_CRU_BASE+ 0x128);
msleep(100);
writel_relaxed(0x00010000, RK2928_CRU_BASE + 0x128);
}
#endif