From a82f7fca8ff1efefd35306b5fbb68bdcdabef155 Mon Sep 17 00:00:00 2001 From: Binyuan Lan Date: Mon, 3 Aug 2020 18:29:13 +0800 Subject: [PATCH] ASoC: rockchip: rk817-codec: Initialize DIGEN_CLKE when reset Solve the problem that LRCK level amplitude is not enough Change-Id: I5fbcd2a10b4c725ea24b73c9c4469027809da003 Signed-off-by: Binyuan Lan --- sound/soc/codecs/rk817_codec.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/rk817_codec.c b/sound/soc/codecs/rk817_codec.c index 3e5196e832ea..ac79784261dc 100644 --- a/sound/soc/codecs/rk817_codec.c +++ b/sound/soc/codecs/rk817_codec.c @@ -252,7 +252,8 @@ static int rk817_reset(struct snd_soc_component *component) { snd_soc_component_write(component, RK817_CODEC_DTOP_LPT_SRST, 0x40); snd_soc_component_write(component, RK817_CODEC_DDAC_POPD_DACST, 0x02); - snd_soc_component_write(component, RK817_CODEC_DTOP_DIGEN_CLKE, 0x0f); + snd_soc_component_write(component, RK817_CODEC_DI2S_CKM, 0x00); + snd_soc_component_write(component, RK817_CODEC_DTOP_DIGEN_CLKE, 0xff); snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x04); snd_soc_component_write(component, RK817_CODEC_APLL_CFG1, 0x58); snd_soc_component_write(component, RK817_CODEC_APLL_CFG2, 0x2d); @@ -1138,7 +1139,7 @@ static const struct regmap_config rk817_codec_regmap_config = { .val_bits = 8, .reg_stride = 1, .max_register = 0x4f, - .cache_type = REGCACHE_NONE, + .cache_type = REGCACHE_FLAT, .volatile_reg = rk817_volatile_register, .writeable_reg = rk817_codec_register, .readable_reg = rk817_codec_register,