From a84097bf1da31d586004e9cfd3553b61f3c722ac Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Mon, 9 Nov 2020 20:44:39 +0800 Subject: [PATCH] drm/rockchip: dsi: add support dual-channel mode with independent PLL Display Pipeline: ---> dsi0 --> dphy_tx0 ---> / | \ / dphy0_pll \ vp1/vp2 --> ---> panel \ dphy1_pll / \ | / ---> dsi1 --> dphy_tx1 ---> Change-Id: I9c975f29e2f40e04a1fac5c163aed0fa7cfb71e3 Signed-off-by: Guochun Huang --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index df0ff0916938..f5d8ae9bf85c 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -1310,6 +1310,9 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) else dw_mipi_dsi_calc_pll_cfg(dsi, lane_rate); + if (dsi->slave && dsi->slave->dphy.phy) + dw_mipi_dsi_set_hs_clk(dsi->slave, lane_rate); + DRM_DEV_INFO(dsi->dev, "final DSI-Link bandwidth: %u x %d Mbps\n", dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes);