From a8a0964ddf6999b7eacf33ae693b6783d44351ae Mon Sep 17 00:00:00 2001
From: Dingxian Wen <shawn.wen@rock-chips.com>
Date: Tue, 31 Aug 2021 19:50:56 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3568-evb2: add lt6911uxc
 configuration

Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
Change-Id: I27e7cd02314fb288a4f553105de1027975b8e9d6
---
 .../dts/rockchip/rk3568-evb2-lp4x-v10.dtsi    | 124 ++++++++++++++++++
 1 file changed, 124 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi
index 7a47fda80a28..187607ec03d0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi
@@ -63,6 +63,13 @@
 		regulator-max-microvolt = <3300000>;
 		vin-supply = <&vcc5v0_sys>;
 	};
+
+	ext_cam_clk: external-camera-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "CLK_CAMERA_24MHZ";
+		#clock-cells = <0>;
+	};
 };
 
 &bt_sound {
@@ -84,6 +91,42 @@
 	status = "okay";
 };
 
+&csi2_dphy_hw {
+	status = "okay";
+};
+
+&csi2_dphy0 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			hdmi_to_mipi_in: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&lt6911uxc_out>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csidphy_out: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&mipi_csi2_input>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+};
+
 /*
  * video_phy0 needs to be enabled
  * when dsi0 is enabled
@@ -168,6 +211,35 @@
 	power-supply = <&vcc3v3_lcd0_n>;
 };
 
+&i2c3 {
+	status = "okay";
+
+	lt6911uxc: lt6911uxc@2b {
+		status = "okay";
+		reg = <0x2b>;
+		compatible = "lontium,lt6911uxc";
+		clocks = <&ext_cam_clk>;
+		clock-names = "xvclk";
+		interrupt-parent = <&gpio4>;
+		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+		power-gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
+		plugin-det-gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
+		hpd-ctl-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>;
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "LT6911UXC";
+		rockchip,camera-module-lens-name = "NC";
+
+		port {
+			lt6911uxc_out: endpoint {
+				remote-endpoint = <&hdmi_to_mipi_in>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+};
+
 &i2c4 {
 	status = "okay";
 
@@ -215,6 +287,39 @@
 	};
 };
 
+&mipi_csi2 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi_csi2_input: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csidphy_out>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi_csi2_output: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&cif_mipi_in>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+};
+
 &video_phy0 {
 	status = "okay";
 };
@@ -394,6 +499,25 @@
 	status = "disabled";
 };
 
+&rkcif_mipi_lvds {
+	status = "okay";
+
+	port {
+		cif_mipi_in: endpoint {
+			remote-endpoint = <&mipi_csi2_output>;
+			data-lanes = <1 2 3 4>;
+		};
+	};
+};
+
+&rkcif_mmu {
+	status = "okay";
+};
+
+&rkcif {
+	status = "okay";
+};
+
 &route_dsi0 {
 	status = "okay";
 	connect = <&vp1_out_dsi0>;