From a8af0afc5ec1c4949fdb0d55edd89391b5b51cb2 Mon Sep 17 00:00:00 2001 From: Yandong Lin Date: Sat, 17 Sep 2022 08:41:27 +0800 Subject: [PATCH] video: rockchip: mpp: fix av1 dec err when multi tiles Do not enable cache_all_e when source is multi tiles. Signed-off-by: Yandong Lin Change-Id: Ie40aac145dfc481f371865efc5e962dd0cfdb451 --- drivers/video/rockchip/mpp/mpp_av1dec.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/video/rockchip/mpp/mpp_av1dec.c b/drivers/video/rockchip/mpp/mpp_av1dec.c index 26ef14a3fe79..0cb625ff3be2 100644 --- a/drivers/video/rockchip/mpp/mpp_av1dec.c +++ b/drivers/video/rockchip/mpp/mpp_av1dec.c @@ -534,11 +534,11 @@ static int av1dec_set_l2_cache(struct av1dec_dev *dec, struct av1dec_task *task) writel_relaxed(AV1_L2_CACHE_SHAPER_EN, dec->reg_base[AV1DEC_CLASS_CACHE] + AV1_L2_CACHE_SHAPER_CTRL); - /* TODO: set exception list */ - - /* multi id enable bit */ - writel_relaxed(0x00000001, dec->reg_base[AV1DEC_CLASS_CACHE] + - AV1_L2_CACHE_RD_ONLY_CONFIG); + /* not enable cache en when multi tiles */ + if (!(regs[10] & BIT(1))) + /* cache all en */ + writel_relaxed(0x00000001, dec->reg_base[AV1DEC_CLASS_CACHE] + + AV1_L2_CACHE_RD_ONLY_CONFIG); /* reorder_e and cache_e */ writel_relaxed(0x00000081, dec->reg_base[AV1DEC_CLASS_CACHE] + AV1_L2_CACHE_RD_ONLY_CTRL);