From a8cf408589711612dd69cda6d3effb086830df8f Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 20 Sep 2017 10:05:51 +0800 Subject: [PATCH] ARM64: dts: rockchip: rk3399: assigned clk_uart4_src parent to PPLL clk_uart4_src default parent is 24M,does not satisfy the fractional divider must set that denominator is 20 times larger than numerator. Change-Id: I21fd9866794e052414a6fdf1d64840ac2a0bb8f2 Signed-off-by: Elaine Zhang --- arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi index 9c2212515c44..14ff440843cb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi @@ -75,8 +75,8 @@ }; &uart4 { - assigned-clocks = <&cru SCLK_UART_SRC>; - assigned-clock-parents = <&cru PLL_GPLL>; + assigned-clocks = <&pmucru SCLK_UART4_SRC>; + assigned-clock-parents = <&pmucru PLL_PPLL>; }; &spdif {