From a919c35a83f2ccbc35b0074fc565f6b7124436ee Mon Sep 17 00:00:00 2001 From: Binyuan Lan Date: Sat, 25 Feb 2023 12:21:14 +0000 Subject: [PATCH] ASoC: rockchip: rk817-codec: don't change APLL_CFG3/DDAC_SR_LMT0 when capture with pdm Change-Id: I1e1b429e64ac6e3fbd5924a6bab4fcfed4a0ae11 Signed-off-by: Binyuan Lan --- sound/soc/codecs/rk817_codec.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/sound/soc/codecs/rk817_codec.c b/sound/soc/codecs/rk817_codec.c index bbd561d1dbe6..dcc85f4e4280 100644 --- a/sound/soc/codecs/rk817_codec.c +++ b/sound/soc/codecs/rk817_codec.c @@ -945,14 +945,16 @@ static int rk817_hw_params(struct snd_pcm_substream *substream, * is before playback/capture_path_put, therefore, we need to configure * APLL_CFG3/DTOP_DIGEN_CLKE/DDAC_SR_LMT0 for different sample rates. */ - snd_soc_component_write(component, RK817_CODEC_APLL_CFG3, apll_cfg3_val); - /* The 0x00 contains ADC_DIG_CLK_DIS and DAC_DIG_CLK_DIS */ - snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, - dtop_digen_clke, 0x00); - snd_soc_component_update_bits(component, RK817_CODEC_DDAC_SR_LMT0, - DACSRT_MASK, dtop_digen_sr_lmt0); - snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, - dtop_digen_clke, dtop_digen_clke); + if (!((substream->stream == SNDRV_PCM_STREAM_CAPTURE) && rk817->pdmdata_out_enable)) { + snd_soc_component_write(component, RK817_CODEC_APLL_CFG3, apll_cfg3_val); + /* The 0x00 contains ADC_DIG_CLK_DIS and DAC_DIG_CLK_DIS */ + snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, + dtop_digen_clke, 0x00); + snd_soc_component_update_bits(component, RK817_CODEC_DDAC_SR_LMT0, + DACSRT_MASK, dtop_digen_sr_lmt0); + snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, + dtop_digen_clke, dtop_digen_clke); + } switch (params_format(params)) { case SNDRV_PCM_FORMAT_S16_LE: